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? mono and colour digital video cmos image sensors cd5410-6410f: rev 3.0 28 september 2000 1/105 vv5410 & vv6410 commercial in confidence the vv5410/vv6410 are multi format digital output imaging devices based on stmicroelectronicss unique cmos sensor technology. both sensors require minimal support circuitry. vv5410 (monochrome) and vv6410 (colourised) produce digital video output. the video streams from both devices contain embedded control data that can be used to enable frame grabbing applications as well as providing input data for the external exposure controller. the pixel array in vv6410 is coated with a bayer colour pattern. this colourised sensor can interface to a range of stmicroelectronics co-processors. a chipset comprising vv6410 and stv0657 will output 8bit yuv or rgb digital video. a usb camera can be realised by partnering vv6410 with stv0672. finally a high quality digital stills camera can be produced by operating vv6410 with stv0680b-001. please contact stmicroelectronics for ordering information on all of these products. both vv5410 and vv6410 are initialised in a power saving mode and must be enabled via i2c control before they can produce video. the i2c allows the master coprocessor to reconfigure the device and control exposure and gain settings. usb systems are catered for with an ultra low power, pin driven, suspend mode. the on board regulator can supply sufficient current drive to power external components, (e.g. the video coprocessor). functional block diagram key features ? 3.3v operation ? multiple video formats available ? pan tilt image feature ? sub sampled image full fov feature ? on board 10 bit adc ? on board voltage regulator ? low power suspend mode for usb systems ? automatic black and dark calibration ? on board audio amplifier ? i2c communications applications ? pc camera ? personal digital assistant ? mobile video phones ? digital stills cameras speci?cations voltage references,voltage regulators and audio amp circuitry digital control logic sda scl data fst lst qck suspend oeb pixel array column adc x-decoder sram line store readout structure y- decoder effective image sizes after colour processing 352 x 288 (cif,pal) 176 x 144 (qcif) pixel resolution up to 356 x 292 pixel size 7.5 m m x 6.9 m m array size 2.73mm x 2.04mm exposure control +81db analogue gain +12db (recommended max) snr c.56db random noise 1.17mv sensitivity (green channel) 2.1v/lux.sec dark current 46mv/sec vfpn 1.2mv supply voltage 3.0v- 6.0v dc +/- 10% supply current 26.2ma (max,cif@30fps) 85 m a (suspend mode) operating temperature (ambient) 0 o c - 40 o c package type 36pin clcc
vv5410 & vv6410 cd5410-6410f-3-0.fm commercial in confidence 2/105 table of contents 1. document revision history ............................................................................................ 4 2. introduction ................................................................................................................. ..... 5 2.1 overview .................................................................................................................... .................... 5 2.2 exposure control............................................................................................................ ................ 5 2.3 digital interface ........................................................................................................... ................... 5 2.4 other features .............................................................................................................. ................. 7 3. operating modes .............................................................................................................. 9 3.1 video timing ................................................................................................................ .................. 9 3.2 pixel array ................................................................................................................. ................... 10 3.3 x-offset and y-offset....................................................................................................... .............. 11 3.4 qcif output modes ........................................................................................................... .......... 16 4. black offset cancellation .............................................................................................. 18 5. dark offset cancellation................................................................................................ 20 6. exposure control ........................................................................................................... 21 7. timed serial interface parameters ............................................................................... 24 8. digital video interface format ...................................................................................... 27 8.1 general description ......................................................................................................... ............. 27 8.2 embedded control data ....................................................................................................... ......... 28 8.3 video timing reference and status/configuration data .................................................................. 31 8.4 detection of sensor using data bus state .................................................................................... .48 8.5 resetting the sensor via the serial interface .............................................................................. 4 8 8.6 resetting the sensor via the resetb pin .................................................................................. 48 8.7 resynchronising the sensor via the resetb pin configured as sinb ....................................... 48 8.8 power-up, low-power and sleep modes ..................................................................................... 50 8.9 suspend mode ................................................................................................................ ............. 52 8.10 data qualification clock, qck .............................................................................................. ....... 52 9. serial control bus .......................................................................................................... 6 0 9.1 general description......................................................................................................... ............. 60 9.2 serial communication protocol ............................................................................................... ..... 60 9.3 data format ................................................................................................................. ................ 60 9.4 message interpretation...................................................................................................... ........... 61 9.5 the programmers model....................................................................................................... ....... 61 9.6 types of messages ........................................................................................................... ........... 82 9.6 types of messages ........................................................................................................... ........... 82 9.7 serial interface timing ..................................................................................................... ............ 85 10. clock signal................................................................................................................ .... 86 11. other features.............................................................................................................. .. 87
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 3/105 cd5410-6410f-3-0.fm 11.1 audio amplifier ............................................................................................................ ................. 87 11.2 voltage regulators ......................................................................................................... .............. 89 11.3 valid supply voltage configurations ........................................................................................ .... 89 11.4 programmable pins .......................................................................................................... ............ 91 12. characterisation details ................................................................................................ 92 12.1 vv5410/vv6410 ac/dc specification ......................................................................................... 9 2 12.2 vv5410/vv6410 optical characterisation data ........................................................................... 92 12.3 vv5410/vv6410 power consumption ......................................................................................... 94 12.4 digital input pad pull-up and pull-down strengths....................................................................... 94 13. pixel defect specification.............................................................................................. 95 13.1 pixel fault definitions .................................................................................................... ............... 95 13.2 stuck at white pixel fault ................................................................................................. ........... 95 13.3 stuck at black pixel fault ................................................................................................. ............ 95 13.4 column / row faults ........................................................................................................ ............ 95 13.5 image array blemishes ...................................................................................................... .......... 96 14. pinout and pin descriptions .......................................................................................... 98 14.1 36pin clcc pinout map...................................................................................................... ......... 98 15. package details (36pin clcc) .................................................................................... 101 16. recommended vv5410/6410 support circuit............................................................. 102 17. evaluation kits (evks) ................................................................................................ 103 18. ordering details............................................................................................................ 104
vv5410 & vv6410 cd5410-6410f-3-0.fm commercial in confidence 4/105 1. document revision history revision date comments 1.0 13/06/2000 ? original release 2.0 06/07/2000 ? package drawing and pin description updated ? optical characterisation data added ? audio description extended ? pixel defect specification added ? product numbering updated ? reference design for bga packaged 410 added ? gain ceiling recommendation 2.1 04/09/2000 ? remove all reference to bga package option 3.0 28/09/2000 ? product maturity moves to mat29 therefore d/s moves to release3.0 table 1 : document revision history
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 5/105 cd5410-6410f-3-0.fm 2. introduction 2.1 overview vv5410/vv6410 is a cif format cmos image sensor. the vv5410 sensor is the basic monochrome device and vv6410 is the colourised variant. the operation of vv5410 and vv6410 is very similar but any differences will be identified and explained. vv6410 can output digital colourised pixel data at frame and line rates compatible with either ntsc or pal video standards. vv5410 and vv6410 contain the same basic video timing modes. table 2 summarises these video modes. the various operating modes are detailed in section 3. important: vv5410 and vv6410s output video data stream only contains raw data. a master co-processor is required to generate a video waveform that can be displayed on a vdu note: the user can also provide a 24 mhz clock, rather than a 16 mhz clock, for the qcif-60fps, cif-25fps and cif-30fps modes, which the sensor then internally divides by 1.5, (see data_format[22]), to give an effective input clock frequency of 16 mhz. 2.2 exposure control vv5410/vv6410 does not include any form of automatic exposure and/or gain control. thus to produce a correctly exposed image the integration period for the pixels, in the sensor array, an exposure control algorithm must be implemented externally. the new exposure values are written to the sensor via the serial interface. 2.3 digital interface the sensors offers a very flexible digital interface, the main components of which are listed below: 1. a tri-stateable 5-wire data bus (d[4:0]) for sending both video data and embedded timing references. 2. 4-wire and 8-wire data bus alternatives available. if the 8-wire option is selected then the fst/lst pins are recon?gured to output data information. 3. a data quali?cation clock, qck, which can be programmable via the serial interface to behave in a number of different ways (tri-stateable). 4. a line start signal, lst (tri-stateable). 5. a frame start signal, fst (tri-stateable). 6. oeb tri-states all 5 data bus lines, d[4:0], the quali?cation clock, qck, lst, fst and d[7]. 7. a 2-wire serial interface (sda,scl) for controlling and setting up the device. mode input clock (mhz) note system clock divisor image size line time ( m s) lines per frame frame rate (fps) qcif - 25 fps 8.00 8 180 x 148 250.00 160 25.00000 qcif - 30 fps 8.00 8 180 x 148 208.00 160 30.04807 qcif - 60 fps 16.00 8 180 x 148 104.00 160 60.09614 cif - 25 fps 16.00 4 356 x 292 125.00 320 25.00000 cif - 30 fps 16.00 4 356 x 292 104.00 320 30.04807 ntsc (3.2 fsc) 28.636360 / 2.5 2 306 x 244 63.555564 525 29.97003 pal (3.2 fsc) 35.46895 / 2.5 2 356 x 292 63.999639 625 25.00014 table 2 : video modes
vv5410 & vv6410 introduction cd5410-6410f-3-0.fm commercial in confidence 6/105 2.3.1 digital data bus along with the pixel data, codes representing the start and end of fields and the start and end of lines are embedded within th e video data stream to allow a co-processor to synchronise with video data the camera module is generating. section 8. defines the format for the output video data stream. 2.3.2 frame grabber control signals to complement the embedded control sequences the data qualification clock (qck), the line start signal (lst) and the field start signal (fst) signals can be independently set-up as follows: 1. disabled 2. free-running. 3. qualify only the control sequences and the pixel data. 4. qualify the pixel data only there is also the choice of two different qck frequencies where one is twice the frequency of the other. 1. fast qck: the falling edge of the clock quali?es every 8, 5 or 4 bit blocks of data that makes up a pixel value. 2. slow qck: the rising edge quali?es 1st, 3rd, 5th, etc. blocks of data that make up a pixel value while the falling edge quali - ?es the 2nd, 4th, 6th etc. blocks of data. for example in 4-wire mode the rising edge of the clock quali?es the most signi?- cant nibbles while the falling edge of the clock quali?es the least signi?cant nibbles. 2.3.3 2-wire serial interface the 2-wire serial interface provides complete control over sensor setup and operation. two serial interface broadcast addresses are supported. one allows all sensors to be written to in parallel while the other allows all sensors and co-processors to be written to in parallel. section 9. defines the serial interface communications protocol and the register map of all the locations which can be accessed via the serial interface. figure 1 : block diagram of vv5410/vv6410 image sensor (5-wire output) output format d[4:0] qck lst fst sda scl oeb clki resetb image format exposure control serial interface offset cancellation digital logic y- decoder vregs, audio amp., & refs photo diode array column adc readout analogue core structure x-decoder sram line store
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 7/105 cd5410-6410f-3-0.fm 2.3.4 sensor/co-processor interface options there are 3 main ways of interfacing to the vv5410/vv6410 sensor based on the above signals: 1. the colour co-processor supplies the sensor clock, clki, and uses the embedded control sequences to synchronise with the frame and line level timings. thus the host and sensor are running off derivatives of the same fundamental clock. to allow the co-processor to determine the best sampling position of the video data, during its power-up sequence the sensor outputs a 101010... sequence on each of its data bus lines for the host to lock on to. 2. the colour co-processor supplies the sensor clock, clki, and uses a free-running qck supplied by the sensor to sample the incoming video data stream. the embedded control sequences are used to synchronise the frame and line level timings. 3. the colour co-processor supplies the sensor clock, clki, and uses fst, lst and the data only mode for qck to synchro- nise to the incoming video data. primarily intended for interfacing to frame grabbers. 2.4 other features 2.4.1 audio ampli?er pins ain and aoutp & aoutn are the input and outputs respectively for an audio amplifier. 2.4.2 voltage regulator the on-chip voltage regulator requires only a few external components to form a fully functional voltage regulator to 3.3v. sda scl d[4:0] clki 1. vv5410/ vv6410 sensor co-processor sda scl d[4:0] qck clki 2. vv5410/ vv6410 sensor co-processor sda scl d[4:0] qck clki 3. vv5410/ vv6410 sensor co-processor lst fst
vv5410 & vv6410 introduction cd5410-6410f-3-0.fm commercial in confidence 8/105 2.4.3 serial interface programmable pins the fst and qck pins are re-configurable to follow the state of 2-bits in a serial register. the user could then use these cont rol bits to control a peripheral device, a motor or shutter mechanism for example.
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 9/105 cd5410-6410f-3-0.fm 3. operating modes 3.1 video timing the video format mode on power-up is cif 30fps by default. after power-up the mode can be changed by a serial interface to write to the video_timing register. the frame/field rate is also programmable via the serial interface. bit [3] of serial register [16] selects between 30 and 25 frames per second for the cif modes and 60/50 fields per second for the digital and analog timing modes. please note that the sensor can exit low power in any of the available video modes. the number of video lines in each frame is the same (320) for both the cif modes. the slower frame rate (25 fps) is implemented by simply extending the line period from 416 pixel periods to 500 pixel periods. table 3 details the setup for each of the video timing modes. a serial write to serial register [16] will force the contents of other registers in the serial interface to change to the appropriate values, regardless of their present state. if for example a diff erent data output mode is required than the default for a particular video mode, a write to the appropriate register after the mode h as changed will restore the desired value. 3.1.1 arbitration registers when the operating video mode is changed a number of serial registers are forced into new states. the complete list is as follows: video mode clock (mhz) system clock divisor video data line length field length data output mode pal (3.2 fsc) 28.636360 / 2.5 2 356 x 292 454 312/313 5-wire ntsc (3.2 fsc) 35.46895 / 2.5 2 306 x 244 364 262/263 5-wire cif - 25 fps 16.0 4 356 x 292 500 320 5-wire cif - 30 fps 16.0 4 356 x 292 416 320 5-wire qcif - 25 fps 8.0 8 180 x 148 250 160 5-wire qcif - 30 fps 8.0 8 180 x 148 208 160 5-wire qcif - 60 fps 16.0 8 180 x 148 208 160 5-wire table 3 : video timing modes arbitrated feature video mode selected/value automatically programmed pal ntsc cif 25fps cif 30fps ptqcif 25fps ptqcif 30fps ssqcif 25fps ssqcif 30fps line length 453 363 499 415 249 207 249 207 ?eld length 311 261 319 319 159 159 159 159 system clock divi- sion 22448888 free running qck note1 yes yes no no no no no no extra black lines note2 yes yes no no no no no no table 4 : arbitration registers
vv5410 & vv6410 operating modes cd5410-6410f-3-0.fm commercial in confidence 10/105 note1: the free running qck, slow by default, is enabled by writing 8h04 to serial register [20]. note2: the contents of the extra black lines are enabled on to the data bus by setting bit [5] of serial register [17]. if bit [0] of serial register [24] is reset, indicating that the preferred coprocessor device is not the vp3 device, (a stmicroelectronics coprocessor), then the extra black lines are enabled by default regardless of the basic video mode selected. the registers that control the image position within the pixel array and also the order in which the pixels are read out have n ot been included in the table as their values are subject to a secondary series of registers. we will discuss the former in sections 2.2 and 2.3. 3.1.2 input clock frequencies it is recommended that a 16 mhz clock is used to generate cif-25fps,cif-30fps and qcif-60fps and that an 8 mhz clock is used to generate qcif-25fps and qcif-30fps, however the sensor can adapt to a range of other input frequencies and still generate the required frame rates. for example, a 24 mhz clock can be used to generate cif-30fps. by setting bit [7] of serial register [22] the sensor can automatically divide the incoming clock by 1.5 by setting bit [7] of serial register [22], such that the interna l clock generator logic will still receive a 16 mhz clock. note that the clock division register is internally an 8 bit value, although the user may only program the lower nibble. the up per nibble is reserved for setting the clock divisor as we change between primary video modes. the lower nibble can be programmed to reduce the effective frame rate within each video mode. the system clock divisor column in table 5 assumes that the programmable pixel clock divisor is set to the default of 0, implementing a divide by 1 of the internal pixel clock. consider the following scenario where a user requires 15 fps cif resolution image. as can be seen there are a wide range of options to achieve the same result. 3.2 pixel array the physical pixel array is 364 x 296 pixels. the pixel size is 7.5 m mby6.9 m m. the image size for ntsc is 306 x 244 pixels, for pal and cif it is 356 x 292 pixels, while for the qcif modes the image size is 180 x 148 pixels. the remaining 4 physical columns on each side of the pal image size prevent columns 1 and 2 in pal/cif modes from being distorted by the edge effects which occur when a pixel is close to the outer edge of the physical pixel array. please note that these columns can be enabled as part of the visible image if the user is operating the sensor in the pantilt qcif mode. figure 3 shows how the 306 x 244 and 180 x 148 sub-arrays are aligned within the bigger 364 x 296 pixel array. the bayer colourisation pattern requires that the top-left corner of the pixel sub-array is always a green 1 pixel. to preserve this baye r colour pattern the ntsc sub-array has been offset relative to the centre of the array. the qcif size images are centrally orientated. image read-out is very flexible. sections 3.3.2 - describe the options available to the user. by default the sensor read out i s configured to be horizontally shuffled non-interlaced raster scan. the horizontally shuffled raster scan order differs from a conventional raster in that the pixels of individual rows are re-ordered, with the odd pixels within a row read-out first, foll owed by the even pixels. this shuffled read-out within a line, groups pixels of the same colour (according to the bayer pattern - figure 2) together, reducing cross talk between the colour channels. this option is on by default and is controllable via the serial interface. the horizontal shuffle option would normally only be selected with the colour sensor variant, vv6410. clk in (mhz) divide by 3/2 enabled? system clock divisor pixel clock divisor pclk (mhz) field rate 8no 4 1 2 15 12 yes 4 1 2 15 16 no 4 2 2 15 24 yes 4 2 2 15 table 5 : system clock divisor options
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 11/105 cd5410-6410f-3-0.fm 3.3 x-offset and y-offset the image information is retrieved from the pixel array via a 2 dimensional address. the x and y address busses count from a starting point described by x-offset, y-offset up to a maximum count in x and y that is determined by the image size. the order of this count and the count step size is dependent upon the special image format parameters described below. the detailed control of the x and y address counters is entirely handled by the sensor logic as can be seen in figure 3 the visible array size is 364 columns by 296 rows. the pal and cif images are sized, 356 columns by 292 rows, thus we have a border of visible pixels that we do not read out if either of these modes are selected. the images that are read out of the sensor are always centred on the array, therefore we allow a border of 4 columns at eithe r end of the image in the x-direction and a border of 2 rows at the top and bottom of the image in the y-direction. the pantilt q cif and ntsc video modes are similarly centred within the full size array. for all the modes except the pantilt qcif the x and y offset coordinates are fixed. if the user selects the pantilt qcif mode t hen they may specify x and y-offsets in the range: ? (xoffset >= 1) and (xoffset <= 185) ? (yoffset >= 5) and (yoffset <= 149) the sensor will automatically clip values outwith the specified ranges. the y addresses less than 5 are reserved for the sensor black lines and the y address greater than 296 are reserved for the sensor dark lines. neither the black lines nor the dark lin es contain visible image data figure 2 : bayer colourisation pattern (vv6410 only) green 1 blue green 2 red odd rows (5, 7, 9,...) even rows (4, 6, 8,...) odd columns (1,3,5,...) even columns (2, 4, 6,...)
vv5410 & vv6410 operating modes cd5410-6410f-3-0.fm commercial in confidence 12/105 blue green green red blue green green red 356 pixels 306 pixels 244 pixels 292 pixels 4 3 2 1 6 8 7 5 6 5 1, 2, 3, 4, 5, 6,... ..., 361, 362, 363, 364 5, 6, 7, 8, 9, 10,... ..., 297, 298, 299, 300 26 pixels 24 pixels 22 pixels 22 pixels blue green green red 10 9 8 7 360 359 358 357 362 361 364 363 296 pixels 364 pixels blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red 180 pixels 148 pixels 88 pixels 72 pixels the colour dyes included in this diagram are only applicable to vv6100. the monochrome device vv5410 has exactly the same readout structure and array size as vv6410 - but no colourised pixels 296 298 297 295 300 299 figure 3 : image readout formats
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 13/105 cd5410-6410f-3-0.fm 3.3.1 image readout parameters the following parameters are available to process the sensor readout: ? shuffle horizontal readout, enabled by setting bit [7] of serial register [17] ? mirror horizontal readout, enabled by setting bit [3] of serial register [22] ? shuffle vertical readout, enabled by setting [2] or serial register [22] ? flip vertical readout, enabled by setting [4] of serial register [22] the effect of each of these parameters is probably best described via a series of diagrams, see sections 3.3.2 - below. although all the above features may be used in conjunction with one another we will only display one special image readout parameter at any one time. 3.3.2 horizontal shuf?e figure 5 is the reference figure that shows the image readout without any of the optional image parameters, shuffle or mirror, selected. figure 5 shows how the image will appear if the horizontal shuffle bit has been selected. note that the even columns, (column 2,4,6 etc), are read out first followed by the odd columns, (1,3,5,7 etc). grgrgrgrgrgr grgrgrgrgrgr where g - green and r - red figure 4 : standard image readout
vv5410 & vv6410 operating modes cd5410-6410f-3-0.fm commercial in confidence 14/105 3.3.3 horizontal mirror figure 6 shows the output image with the horizontal mirror feature enabled. note that the columns are read out in reverse order . 3.3.4 vertical flip figure 7 shows the output image with the vertical flip feature enabled. note that the even rows (rows 2,4,6 etc), are read out first rrrrrrgggggg grgrgrgrgrgr where g - green and r - red figure 5 : horizontal shuf?e enabled grgrgrgrgrgr rgrgrgrgrgrg where g - green and r - red figure 6 : horizontal mirror enabled
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 15/105 cd5410-6410f-3-0.fm followed by the odd rows, (rows 1,3,5 etc) 3.3.5 vertical flip figure 3.4 shows the output image with the vertical flip feature enabled. note that the rows are read out in reverse order. b g b g b g b g b g g g g g g b b b b b where g - green and b - blue figure 7 : vertical shuf?e enabled b g b g b g b g b g g b g b g b g b g b where g - green and b - blue figure 8 : vertical flip enabled
vv5410 & vv6410 operating modes cd5410-6410f-3-0.fm commercial in confidence 16/105 3.4 qcif output modes vv5410/vv6410 has two qcif output modes, pan/tilt qcif (ptqcif) and sub sampled qcif (ssqcif), both of which have the same output format. the data contained within the active qcif image differs between the sub sampled and pan tilt modes. as the qcif mode contains a quarter of the data of the cif mode, the effective pixel clock can be run at a quarter of the rate. th is means that in cif mode a system clock of 16mhz will produce a field rate of 30fps, whereas in qcif mode a system clock of only 8mhz is required to produce the same field rate. note that the sensor divides the system clock internally by 4 for cif mode and 8 for qcif mode. if the user supplied the sensor with a 16mhz system clock and selected qcif mode then a field rate of 60fps is possible. 3.4.1 pan/tilt qcif in this mode the qcif image is generated by outputting a cropped portion of the cif image as illustrated in figure 9. when the pan-tilt qcif video mode is initially selected the image will be horizontally and vertically justified in the within the full s ize array (364 pixels by 292 pixels). the coordinates which define the top left corner of the qcif portion of the array to be output are defined by the x-offset & y-offset parameters in serial registers [88 - 91] inclusive. the x-offset and y-offset parameters are subject to minimum and maximum values which are set according to the video output mode (horizontal shuffle etc). any clipping (against a maximum) or clamping (against a minimum) will be automatically controlled by the sensor logic. regardless of whether any of the shuffle/mirror modes have been selected the user should always identify the top left corner coordinates as the x-offset and y-offset. to preserve the bayer pattern at the sensor output the first pixel image of the image should always be green followed by red. if the x or y offsets are adjusted by a single step, i.e. adjust the x-offset from n to n+1, then this pattern will be corrupted. the user should always write an odd number to the x and y offset registers and this will preserve the bayer pattern. the 5410, monochrome sensor is unaffected by such an adjustment to the x-offset coordinate, as the pixels do not contain any colour information. figure 9 : pan/tilt qcif image format 180 pixels 148 pixels y-offset x-offset 364 pixels 292 pixels qcif image
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 17/105 cd5410-6410f-3-0.fm 3.4.2 sub-sampled qcif in this mode the qcif image is generated by sub-sampling the cif image in groups of 4 to preserve the bayer pattern with every second group of pixels & lines skipped as illustrated in figure 10. although the former would not necessarily apply to a monochrome sensor the same address sequence is preserved. vv5410 users should ignore the colour references in figure 10. due to the crude nature of the sub-sampling, the resultant output image will be of inferior quality but contains full field of view and is intended for use in gesture recognition applications or perhaps as a preview option before switching to pan tilt qcif mode t o view the required scene region in more detail. figure 10 : sub-sampled qcif image format blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red bayer colourised pixel array sub-sampled bayer colourised pixel array
vv5410 & vv6410 black offset cancellation cd5410-6410f-3-0.fm commercial in confidence 18/105 4. black offset cancellation in order to produce a high quality output image from vv6410 it is important to maximise the dynamic range of the video output. this can be achieved by accurately controlling the video signal black level. within the sensor array of vv6410 there are a number of lines that are specified to be black, that is they are exposed to the incident light but they are always held in minimum exposure. vv6410 also has a number of dark lines, that is lines that are integrated for the same length of time as the visible lines but the pixels within these dark lines are shielded from incident light by an opaque material (e.g. metal 3). the diagram below shows where the different types of lines that appear within the full array. vv5410/vv6410 can perform automatic black offset cancellation. vv5410/vv6410 contains an algorithm that monitors the level of the designated black pixels and applies a correction factor, if required, to provide an ideal black level for the video stre am. the user can control the application of the offset cancellation parameter. the internally calculated offset can be applied to t he video stream or alternatively an externally calculated offset can be applied or finally there is the option of applying no offset at all. details of how to select the aforementioned modes can be found in subsubsection 9.5.5. the black offset cancellation algorithm accumulates data from the centre 2 of the 4 physical black lines. the internal cancellation algorithm uses a leaky integrator model to control the size of the calculated offset. the leaky integrator model takes as input the current offset plus a shifted version of the error between the ideal black level and the current offset. the magnitude of the shift in the error is programmable. it is also possible to control the range of pixel values that will inhibit a change in the calculated offset. a narrow band (128 +/- 2 codes) or a wide band (128 +/- 4 codes) can be selected. if the latter is selected and the pixel average figure 11 : physical position of black and dark lines 364 pixels 296 pixels dark lines 8 pixels 4 pixels black lines visible pixel array
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 19/105 cd5410-6410f-3-0.fm returned in the current field lies between 124 and 132 then the offset cancellation will remain unchanged. following a gain change, or when exitting low-power, sleep or suspend modes, the internal (19bit) offset register will be reset to the default resulting in an automatic black offset of -64.
vv5410 & vv6410 dark offset cancellation cd5410-6410f-3-0.fm commercial in confidence 20/105 5. dark offset cancellation vv5410/vv6410 performs dark line offset cancellation as well as black line offset cancellation. a dark line is shielded from incident light by an opaque material such as metal 3 (as an example) but these lines will be exposed to incident light for the same length of time as the visible pixels. if the dark pixels are completely shielded from light then no incident light should reach the pixels and the pixels will produce the same digital code as the black pixels, i.e. 128 internally (therefore 64 externally). th e algorithm used to calculate the dark offset cancellation is identical to that used to calculate the black offset cancellation, however the dark algorithm does assume that the dark pixels have already been black corrected therefore the target dark average is 64 thus the dark offset cancellation is 0 by default. the dark offset cancellation algorithm is configured by the dark offset cancellation setup register, [46], see subsubsection 9. 5.3. the only parameter in this that is different from the corresponding table that configures the black offset cancellation algorit hm is the control bit, [bit2], that determines the number of dark lines that are to be used by the cancellation algorithm. it is poss ible to select half of the total number of available dark lines to be used to calculate the dark offset cancellation setting. when the former is selected the dark lines used by the algorithm are always preceeded by another dark line, thereby giving extra immunity from damaging edge effects that may occur on lines close to the edge of the shield material. it should be noted that the black and dark offset cancellation are completely independent. for example it is possible for the u ser to select internal automatic black offset cancellation but to opt for no dark offset cancellation or indeed choose to perform the dark offset cancellation externally.
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 21/105 cd5410-6410f-3-0.fm 6. exposure control 6.1 calculating exposure period the exposure time, comprising coarse and fine components, for a pixel and the analogue gain are programmable via the serial interface. the coarse exposure value sets the number of complete lines a pixel exposes for, while the fine exposure sets the number of additional pixel clock cycles a pixel integrates for. the sum of the two gives the overall exposure time for the pixel array. exposure time = ((coarse setting x line period) + (fine setting)) x (clki clock period) x clock divider ratio note1 note1: clock divider ratio = 1/(basic clock division * optional pixel clock divisor) default clock divider ratio as follows: (optional pixel clock divisor = 1) ? pal/ntsc - 1/2 ? cif - 1/4 ? qcif - 1/8 the maximum coarse and fine exposure settings are a function of the field and line lengths respectively. the maximum coarse exposure is current field length - 1 and the maximum fine exposure is current line length - fixed offset, see below. if an exposure value is requested that is beyond the maximum then the applied exposure setting will be clipped to the current maximum. 6.2 gain components the analogue gain in vv5410/vv6410 is programmed via the 8 bit gain register[36]. the analogue gain comprises 2 components, capacitive gain, (set by the ms nibble), and current gain, (set by the ls nibble). it is strongly recommended that the capacitive gain setting is left at the default value of 4b1111. table 7 details the available gain settings in 9bit, (pal or n tsc), and 10bit, (cif or qcif), modes. we assume that mode_select[24], bit1 is 0. gain[7:0] is the value programmed in register[36]. the ls nibble of the gain value is limited to 4he, with 4hf not permitted. video mode fine exposure offset (pcks) ntsc 51 pa l 8 6 cif 51 qcif 23 table 6 : fine exposure offset the current revision of vv5410/vv6410 in the following modes of operation: vp3 mode (off), qcif and pal (video mode) has an error in the application of coarse exposure. please contact stmicroelectronics for more details.
vv5410 & vv6410 exposure control cd5410-6410f-3-0.fm commercial in confidence 22/105 note: the relationship between the programmed gain value as written to register[36] and the igain (current gain) and cgain (capacitive gain) is as follows: igain if mode_select[24], bit 1 is set then igain[3:0] is the inverse of gain[3:0], i.e. if gain[3:0] = 6, igain[3:0] = 9. if mode_select[24], bit 1 is reset then igain[3:0] is the inverse of the mirror of gain[3:0], i.e. bit 3 of igain is the invers e of bit 0 of gain, i.e. gain = 4 and igain = 13. cgain cgain is a 6 bit value therefore we have to pad the 4 bits of the gain register. in 10bit modes cgain[1:0] is fixed at 2b11 an d cgain[5:2] is set to gain[7:4]. in the 9bit modes cgain[1:0] is also set to 2b11, however cgain[5:2] is set to gain[7:4] divid ed by 2, thus gain[7:4] = 4b1111 gives cgain[5:0] = 6b011111. 6.2.1 recommended gain settings to ensure optimum sensor performance it is recommended that the igain setting, controlled by the ls nibble of serial register[36 10 ], be limited to 12. 6.3 clock division although the clock divisor register is an 8 bit register the user only has write access to the lower 4 bits as described above. the upper 4 bits of the register are altered automatically when the video mode is changed by writing to setup0[16] register. the upper 4 bits are pre-programmed as follows: 10bit adc mode 9bit adc mode gain[7:0] igain[3:0] cgain[5:0] overall gain gain[7:0] igain[3:0] cgain[5:0] overall gain 8hfe 1 (0001 2 ) 63 8.000 8hfe 1 (0001 2 ) 31 8.000 8hfd 2 (0010 2 ) 63 5.333 8hfd 2 (0010 2 ) 31 5.333 8fc 3 (0011 2 ) 63 4.000 8fc 3 (0011 2 ) 31 4.000 8hfb 4 (0100 2 ) 63 3.200 8hfb 4 (0100 2 ) 31 3.200 8hfa 5 (0101 2 ) 63 2.667 8hfa 5 (0101 2 ) 31 2.667 8hf9 6 (0110 2 ) 63 2.2857 8hf9 6 (0110 2 ) 31 2.2857 8hf8 7 (0111 2 ) 63 2.0000 8hf8 7 (0111 2 ) 31 2.0000 8hf7 8 (1000 2 ) 63 1.7778 8hf7 8 (1000 2 ) 31 1.7778 8hf6 9 (1001 2 ) 63 1.6000 8hf6 9 (1001 2 ) 31 1.6000 8hf5 10 (1010 2 ) 63 1.4545 8hf5 10 (1010 2 ) 31 1.4545 8hf4 11 (1011 2 ) 63 1.3333 8hf4 11 (1011 2 ) 31 1.3333 8hf3 12 (1100 2 ) 63 1.2308 8hf3 12 (1100 2 ) 31 1.2308 8hf2 13 (1101 2 ) 63 1.1429 8hf2 13 (1101 2 ) 31 1.1429 8hf1 14 (1110 2 ) 63 1.0667 8hf1 14 (1110 2 ) 31 1.0667 8hf0 15 (1111 2 ) 63 1.0000 8hf0 15 (1111 2 ) 31 1.0000 table 7 : analogue gain settings
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 23/105 cd5410-6410f-3-0.fm 6.4 updating exposure, gain and clock division settings although the user can write a new exposure, gain or clock division parameter at any point within the field the sensor will only consume these new external values at a certain point. the exceptions to this behaviour are when the user has selected immediate update of gain and clock division. if the user has selected the former then the new gain or clock division value will be applied as soon as the serial interface message has completed. the fine and coarse exposure values are always written in a timed manner. there are a number of update pending flags available to the user (see status0 reg[2] for details) that allows the user to detect when the sensor has consumed one of the timed parameters. in the next section of this document we will detail all the timed parameters and describe when they are updated. it is important to realise that there is a 1 frame latency between a new exposure value being applied to the sensor array and t he results of this new exposure value being read-out. the same latency does not exist for the gain value. to ensure that the effect of the new exposure and gain values are coincident the sensor delays the application of the new gain value by approximately one frame relative to the application of the new exposure value. if the user is using the autoincrement option in the serial interface when writing a new series of exposure/gain and clock divi sion parameters then it is important to ensure that the sensor receives the complete message bunch before updating any of the parameters. it is also important that the timed parameters are updated in the correct order, we will discuss this fully in the next section. if an autoincrement message sequence is in progress but we have reached the point in the field timing where the gain value would normally be updated, we actually inhibit the update. we inhibit the update to ensure that the gain change is not passed to the sensor while a change in the exposure is still pending. video mode register[37], bits[7:4] effective system clock divisor cif 4b0001 divide clki/clkip by 4 qcif 4b0011 divide clki/clkip by 8 pal/ntsc 4b0000 divide clki/clkip by 2 table 8 : system clock divisor options
vv5410 & vv6410 timed serial interface parameters cd5410-6410f-3-0.fm commercial in confidence 24/105 7. timed serial interface parameters the previous section, exposure control, introduced the concept of a timed parameter, that is information that is written via the serial interface but will not be used immediately by the sensor, rather there will be a delay before the information is passed to the internal registers (referred to as the working registers) from the serial interface registers (referred to as the shadow registers). it is the contents of the working registers that will determine sensor behaviour. the architecture of vv5410/6410 requires that many of the programmable registers are handled in such a manner. this section will identify all these registers, describe what they are all used for and then go on to explain when they are all updated. 7.1 listing and categorizing the parameters the timed parameters are split into 6 categories as follows: ? fine exposure ? coarse exposure ? clock division ? gain ? pan parameter ? tilt parameter ? video timing there is a pending flag for each of the above categories. these flags are stored in status0 register[2]. if one of the flags is high this indicates that the working register/s controlled by that flag have yet to be updated from the according shadow register/s. this feedback information could be useful if a user is, for example, attempting to write an exposure controller. the status of the pending flags allows accurate timing of the serial interface communications. 7.1.1 fine exposure the fine exposure category simply comprises registers[32,33]. 7.1.2 coarse exposure the coarse exposure category simply comprises registers[34,35]. 7.1.3 clock division the clock division category simply comprises register[37]. 7.1.4 gain the gain category simply comprises register[36]. 7.1.5 pan parameter the pan parameter category comprises the following registers: ? setup0[16] (the pan_pend flag will only be set if the subsampled qcif mode is entered or exited) ? setup1[17] (the pan_pend flag will only be set if the hshuffle control bit is changing state) ? data_format[22] (the pan_pend flag will only be set if the hmirror control bit is changing state) ? x-offset[87,88] (the pan_pend flag set unconditionally) 7.1.6 tilt parameter the tilt parameter category comprises the following registers: ? setup0[16] (the tilt_pend flag will only be set if the subsampled qcif mode is entered or exited) ? data_format[22] (the tilt_pend flag will be set if the hshuffle control bit or the hmirror control bit is changing state) ? y-offset[89,90] (the tilt_pend flag set unconditionally)
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 25/105 cd5410-6410f-3-0.fm 7.1.7 video timing parameter the video timing parameter category comprises all the other shadow/working register pairs. the video timing parameter update pending flag will be unconditionally set if any of the following registers are written to: ? setup0[16] ? setup1[17] ? fg_mode[20] ? data_format[22] ? op_format[23] ? mode_select[24] ? dark pixel offset[44,45] ? dark pixel cancellation setup register ? black pixel offset[44,45] ? black pixel cancellation setup register ? line length[82,83] ? field length[97,98] 7.2 timed parameter update points the timed parameter categories are updated as follows: note: we refer to odd and even fields in the table 9 below. in a video mode like cif or qcif the fields are all identical in le ngth, we still have to be able to differentiate between fields to enable correct updating of register parameters. the order that the above timed parameters are updated is critical. let us assume that all the pending flags are set, i.e. we ha ve written to at least one register in each category. the working registers will be updated in the following order: 1. coarse exposure 2. tilt parameters timed parameter category updated point ?ne exposure conditional on a change pending in the line length register. line length change pending : update ?ne exposure at the odd to even ?eld transition line length change not pending : update ?ne exposure during the start of active video (sav) region of the end of frame (eof) line (the line that follows the last line of active video) in the odd ?eld. coarse exposure updated during the sav region of the ?rst dark line in an odd ?eld clock division updated at the odd to even ?eld transition gain updated during the sav region of the eof line in the odd ?eld pan parameter updated during the sav region of the eof line in the odd ?eld tilt parameter updated during the sav region of the ?rst visible line in an odd ?eld video timing updated at the odd to even ?eld transition table 9 : timed parameter update points
vv5410 & vv6410 timed serial interface parameters cd5410-6410f-3-0.fm commercial in confidence 26/105 3. gain, pan parameters and conditionally the fine exposure (see table 9 for details) 4. clock division, video timing parameters and conditionally the fine exposure (see table 9 for details)
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 27/105 cd5410-6410f-3-0.fm 8. digital video interface format 8.1 general description the video interface consists of a bidirectional, tri-stateable 5-wire data bus. the nibble transmission is synchronised to the rising edge of the system clock (figure 31). digital video data may be either 8 or 10 bits per sample, and can be transmitted in one of the following ways: 10-bit data 1. a series pair of 5-bit nibbles, most signi?cant nibble ?rst, on 5 wires. 2. an 8-bit number e.g. line code. line numbers and status line data is padded with 00 in the least signi?cant two bits to make up a 10-bit value. 8-bit data 1. a single 8 bit byte over 8 output wires note . 2. a series pair of 4-bit nibbles, most signi?cant nibble ?rst, on 4 wires. 3. the top 8-bits of a 10-bit value e.g. pixel data or line averages is used as the 8-bit equivalent. note: if the 8-wire output mode has been selected then the normal fst/lst pin function is sacrificed as these pins are required to output data information in the following description the 4-wire mode is used as an example. the 5-wire mode can be viewed as a variant of the 4-wire mode. data is output on the least significant data wires available. e.g. in 4-wire mode, data is output on data wires d[3:0] while in read-out order progressive scan (non-interlaced) form of encoding uniformly quantised, pcm, 8/10 bits per sample correspondence between video signal levels and quantisation levels: the internal10-bit pixel data is clipped to ensure that 0 h and 3ff h (5 wire) or ff h (4/8 wire) values do not occur when pixel data is being output on the data bus. 10-bit data 8-bit data pixel values 1 to 1022 pixel values 1 to 254 black level 64 black level 16 table 10 : video encoding parameters figure 12 : possible output modes 4 - wire output mode d 9 ,d 8 ,d 7 ,d 6 d 5 ,d 4 ,d 3 ,d 2 d 5 ,d 4 ,d 3 ,d 2 d 9 ,d 8 ,d 7 ,d 6 8-bit pixel data 10-bit pixel data 5 - wire output mode d 9 ,d 8 ,d 7 ,d 6 ,d 5 d 4 ,d 3 ,d 2 ,d 1 ,d 0 d 4 ,d 3 ,d 2 ,d 1 ,d 0 d 9 ,d 8 ,d 7 ,d 6 ,d 5 8- wire output mode d 9 ,d 8 ,d 7 ,d 6 ,d 5 ,d 4 ,d 3 ,d 2 d 9 ,d 8 ,d 7 ......... ....d 2 ,d 1 ,d 0
vv5410 & vv6410 digital video interface format cd5410-6410f-3-0.fm commercial in confidence 28/105 5-wire mode data is output on d[4:0]. multiplexed with the sampled pixel data is control information including both video timing references, sensor status/configuration data and the pixel average from the current line. video timing reference information takes the form of field start characters, line start characters, end of line characters and a line counter. where hexadecimal values are used, they are indicated by a subscript h, such as ff h ; other values are decimal. 8.2 embedded control data to distinguish the control data from the sampled video data all control data is encapsulated in embedded control sequences. these are 6 bytes long and include a combined escape/sync character sequence, 1 control byte (the command byte) and 2 bytes of supplementary data. to minimise the susceptibility of the embedded control data to random bit errors redundant coding techniques have been used to allow single bit errors in the embedded control words to be corrected. however, more serious corruption of control words or the corruption of escape/sync characters cannot be tolerated without loss of sync to the data stream. to ensure that a loss of sync is detected a simple set of rules has been devised. the four exceptions to the rules are outlined below: 1. data containing a command word that has two bit errors. 2. data containing two end of line codes that are not separated by a start of line code. 3. data preceding an end of ?eld code before a start of frame code has been received. 4. data containing line that do not have sequential line numbers (excluding the end of ?eld line). if the host detects one of these violations then it should abandon the current field of video 8.2.1 the combined escape and sync character each embedded control sequence begins with a combined escape and sync character that is made up of three words. the first two of these are ff h ff h - constituting two words that are illegal in normal data. the next word is 00 h - guaranteeing a clear signal transition that allows a host to determine the position of the word boundaries in the serial stream of nibbles. combined escape and sync characters are always followed by a command byte - making up the four byte minimum embedded control sequence. 8.2.2 the command word the byte that follows the combined escape/sync characters defines the type of embedded control data. three of the 8 bits are used to carry the control information, four are parity bits that allow the host to detect and correct a certain level of erro rs in the transmission of the command words, the remaining bit is always set to 1 to ensure that the command word never has the value 00 h . the coding scheme used allows the correction of single bit errors (in the 8-bit sequence) and the detection of 2 bit errors the three data bits of the command word are interpreted as shown in figure 13.the even parity bits are based on the following relationships: 1. an even number of ones in the 4-bit sequence (c 2 , c 1 , c 0 and p 0 ). 2. an even number of ones in the 3-bit sequence (c 2 , c 1 , p 1 ). 3. an even number of ones in the 3-bit sequence (c 2 , c 0 , p 2 ). 4. an even number of ones in the 3-bit sequence (c 1 , c 0 , p 3 ). table 13 shows how the parity bits maybe used to detect and correct 1-bit errors and detect 2-bit errors. 8.2.3 supplementary data the last 2 bytes of the embedded control sequence contains supplementary data. the are two options: 1. the last 2 bytes of the sav 6 byte sequence contain the current 12-bit line number. the 12-bit line number is packaged up by splitting it into two 6-bit values. each 6-bit value is then converted into an 8-bit value by adding a zero to the start and an odd word parity bit at the end. 2. the 5th byte of the eav sequence contains a pixel average for that line either based upon the middle 256 pixels if the cif,pal or ntsc video modes are selected or the middle 128 pixels if the qcif video mode is selected. the ?nal byte is ff h . note: in 5-wire mode, the embedded control data is calculated as detailed above and output as the most significant 8-bits. the least significant 2-bits are padded with zero.
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 29/105 cd5410-6410f-3-0.fm note1: this code is only generated in the pal or ntsc video modes note2: this code is only generated in the pal or ntsc video modes we include table 12 to show how the 8 bit control codes are mapped onto the output data bits in the 5 wire mode. table 12 : mapping 8bit control codes to 5 wire output mode line code nibble x h (1 c 2 c 1 c 0 ) nibble y h (p 3 p 2 p 1 p 0 ) end of line 1000 2 (8 h ) 0000 2 (0 h ) blank line (bl) 1001 2 (9 h ) 1101 2 (d h ) black line (bk) 1010 2 (a h ) 1011 2 (b h ) visible line (vl) 1011 2 (b h ) 0110 2 (6 h ) start of even field (soef) 1100 2 (c h ) 0111 2 (7 h ) end of even field (eoef) 1101 2 (d h ) 1010 2 (a h ) start of odd field (soof) note1 1110 2 (e h ) 1100 2 (c h ) end of odd field (eoof) note2 1111 2 (f h ) 0001 2 (1 h ) table 11 : embedded line codes line code most signi?cant nibble data[4:0] least signi?cant nibble data[4:0] end of line 1_0000 2 (10 h ) 0_0000 2 (00 h ) blank line (bl) 1_0011 2 (13 h ) 1_0100 2 (14 h ) black line (bk) 1_0101 2 (15 h ) 0_1100 2 (0c h ) visible line (vl) 1_0110 2 (16 h ) 1_1000 2 (18 h ) start of even field (soef) 1_1000 2 (18 h ) 1_1100 2 (1c h ) end of even field (eoef) 1_1011 2 (1b h ) 0_1000 2 (08 h ) start of odd field (soof) 1_1101 2 (1d h ) 1_0000 2 (10 h ) end of odd field (eoof) 1_1110 2 (1e h ) 0_0100 2 (04 h ) parity checks comment p 3 p 2 p 1 p 0 4444 code word un-corrupted 4448 p 0 corrupted, line code ok 4484 p 1 corrupted, line code ok 4844 p 2 corrupted, line code ok table 13 : parity checking
vv5410 & vv6410 digital video interface format cd5410-6410f-3-0.fm commercial in confidence 30/105 8444 p 3 corrupted, line code ok 8848 c 0 corrupted, invert sense of c 0 8488 c 1 corrupted, invert sense of c 1 4888 c 2 corrupted, invert sense of c 2 all other codes 2-bit error in code word. parity checks comment p 3 p 2 p 1 p 0 table 13 : parity checking
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 31/105 cd5410-6410f-3-0.fm 8.3 video timing reference and status/con?guration data each frame of video sequence comprises 2 fields. each field of data is constructed of the following sequence of data lines. figure 13 : embedded control sequence command (line code) supplementary data (i) line number (l 11 msb) output in sav or (ii) pixel average output in eav (4-wire used as example, p 7 msb) odd word parity 0 1 2 3 4 5 6 7 bit nibble d 0 = f h nibble d 1 = f h p 6 p 7 p 5 p 4 l 11 0 l 10 l 9 l 7 l 8 l 6 p p 2 p 3 p 1 p 0 1 1 1 1 1 1 1 1 nibble d 2 nibble d 3 0 1 2 3 4 5 6 7 bit l 5 0 l 4 l 3 l 1 l 2 l 0 p nibble d 0 nibble d 1 0 1 2 3 4 5 6 7 bit c 2 1 c 1 c 0 p 2 p 3 p 1 p 0 nibble y h nibble x h 4-wire output mode 8-bit data escape/sync sequence d 0 d 1 d 2 d 3 y h x h 0 h 0 h f h f h f h f h ff h ff h 00 h xy h d 3 d 2 d 1 d 0 5-wire output mode 00 h 00 h 1f h 1f h 1f h 1f h nibble d 3 nibble d 2
vv5410 & vv6410 digital video interface format cd5410-6410f-3-0.fm commercial in confidence 32/105 1. a start of ?eld line 2. a number of black lines 3. a number of blank (or dark) lines 4. a number active video lines 5. an end of ?eld line 6. a number of blank or black lines table 14 details the number of each type of data lines for ntsc, pal, cif and qcif output formats. each line of data starts with an embedded control sequence that identifies the line type (as outlined in table 14). the control sequence is then followed by two bytes that contain a coded line number. the line number sequences starts with the start-of-frame line at 00 h and increments one per line up until the end-of-frame line. each line is terminated with an end-of-line embedded control sequence. the line start embedded sequences must be used to recognise visible video lines as a number of null bytes may be inserted between successive data lines. there are a series of figures (figure 14 - figure 25) on the following pages that show line type construction of the fields in each video format ntsc pa l cif qcif vp3 mode on off on off on off on off extra black lines on off n/a on off n/a on off n/a on off n/a 1st field start of field line 1 1 1 1 1 1 1 1 1 1 1 1 black lines 8 2 8 8 2 16 8 2 16 8 2 8 blanking lines 1 7 0 1 7 0 1 7 0 1 7 0 dark lines 0 0 8 0 0 2 0 0 10 0 0 2 active video lines 244 244 244 292 292 292 292 292 292 148 148 148 end of field line 1 1 1 1 1 1 1 1 1 1 1 1 blanking lines 0 7 0 0 9 0 0 17 0 0 1 0 black lines 7 0 0 9 0 0 17 0 0 1 0 0 total 262 262 262 312 312 312 320 320 320 160 160 160 2nd field start of field line 1 1 1 1 1 1 1 1 1 1 1 1 black lines 8 2 8 8 2 16 8 2 16 8 2 8 blanking lines 1 7 0 1 7 0 1 7 0 1 7 0 dark lines 0 0 8 0 0 2 0 0 10 0 0 2 active video lines 244 244 244 292 292 292 292 292 292 148 148 148 end of field line 1 1 1 1 1 1 1 1 1 1 1 1 blanking lines 0 8 0 0 10 0 0 17 0 0 1 0 black lines 8 0 1 10 0 1 17 0 0 1 0 0 total 263 263 263 313 313 313 320 320 320 160 160 160 table 14 : field and frame formats
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 33/105 cd5410-6410f-3-0.fm of the available video modes in vv5410/vv6410. 8.3.1 blank lines in addition to padding between data lines, actual blank data lines may appear in the positions indicated above. these lines begin with start-of-blank-line embedded control sequences and are constructed identically to active video lines except that they will contain only blank bytes, 07 h , (expressed as 01c h in 10bit form). 8.3.2 black line timing the black lines (which are used for black offset calculation) are identical in structure to valid video lines except that they begin with a start-of-black line code and contain either information from the sensor black lines or blanking data. by default vp3 mode (see mode_select[24] for details) is selected. it is an option in any of the vp3 modes to select the additional black lines to be output (line 3-8). if the vp3 mode is not selected then all the black lines are enabled - no blank lines are output. internally there is the concept of dark lines - to be used for dark offset cancellation (see following diagrams to identify the ir position within the frame timing model), however externally the dark lines share the same line type code as the black lines. 8.3.3 padding lines and fields the user may choose to extend the inter-field period by increasing the field length by writing to serial registers 97 & 98. in this event, the appropriate number of additional black or blank lines is inserted between the end of field (eof) line and the start of field (sof) line. this means that the distance between sof and eof will remain constant. the user can also extend the line length by writing to serial registers 82 and 83. the line length padding is inserted after the eav sequence, ensuring that the distance between the sav and eav sequences will remain constant.
vv5410 & vv6410 digital video interface format cd5410-6410f-3-0.fm commercial in confidence 34/105 figure 14 : ntsc field and frame formats - vp3 mode on, extra black lines off 8 blanking lines 262 2 black lines start of 2nd field line end of 2nd field line 7 blanking lines 244 visible lines 8 blanking lines 0 2nd field = 263 lines frame = 525 lines 1 0 2 3 9 10 11 253 251 252 12 254 262 255 2 black lines start of 1st field line end of 1st field line 7 blanking lines 244 visible lines 7 blanking lines 1st field = 262 lines 1 0 2 3 9 10 11 253 251 252 12 254 261 255 start of 1st field line 8 8
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 35/105 cd5410-6410f-3-0.fm figure 15 : ntsc field and frame formats - vp3 mode on, extra black lines on 8 blanking lines 262 8 black lines start of 2nd field line end of 2nd field line blanking line 244 visible lines 8 black lines 0 2nd field = 263 lines frame = 525 lines 1 0 2 3 9 10 11 253 251 252 12 254 262 255 8 black lines start of 1st field line end of 1st field line blanking line 244 visible lines 7 black lines 1st field = 262 lines 1 0 2 3 9 10 11 253 251 252 12 254 261 255 start of 1st field line 8 8
vv5410 & vv6410 digital video interface format cd5410-6410f-3-0.fm commercial in confidence 36/105 end of 2nd field line 261 end of 2nd field line 8 dark lines 244 visible lines 17 18 260 258 259 19 261 16 9 262 1 black line figure 16 : ntsc field and frame formats - vp3 mode off 8 black lines start of 2nd field line 0 2nd field = 263 lines frame = 525 lines 1 0 2 3 8 black lines start of 1st field line end of 1st field line 8 dark lines 244 visible lines 1st field = 262 lines 1 0 2 3 9 17 18 260 258 259 19 261 start of 1st field line 8 16 10 262 1 black line 8
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 37/105 cd5410-6410f-3-0.fm figure 17 : pal field and frame formats - vp3 mode on, extra black lines off 10 blanking lines 312 2 black lines start of 2nd field line end of 2nd field line 7 blanking lines 292 visible lines 10 blanking lines 0 2nd field = 313 lines frame = 625 lines 1 0 2 3 9 10 11 301 299 300 12 302 312 303 2 black lines start of 1st field line end of 1st field line 7 blanking lines 292 visible lines 9 blanking lines 1st field = 312 lines 1 0 2 3 9 10 11 301 299 300 12 302 311 303 start of 1st field line 8 8
vv5410 & vv6410 digital video interface format cd5410-6410f-3-0.fm commercial in confidence 38/105 figure 18 : pal field and frame formats - vp3 mode on, extra black lines on 10 black lines 312 8 black lines start of 2nd field line end of 2nd field line blanking line 292 visible lines 10 black lines 0 2nd field = 313 lines frame = 625 lines 1 0 2 3 9 10 11 301 299 300 12 302 312 303 8 black lines start of 1st field line end of 1st field line blanking line 292 visible lines 9 black lines 1st field = 312 lines 1 0 2 3 9 10 11 301 299 300 12 302 311 303 start of 1st field line 8 8
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 39/105 cd5410-6410f-3-0.fm figure 19 : pal field and frame formats - vp3 mode off 312 start of 2nd field line 0 2nd field = 313 lines frame = 625 lines 0 16 black lines start of 1st field line end of 1st field line 2 dark lines 292 visible lines 1st field = 312 lines 1 0 2 3 17 19 20 310 308 309 21 311 start of 1st field line 16 1 black line 18 15 14 16 black lines end of 2nd field line 2 dark lines 292 visible lines 1 2 3 17 19 20 310 308 309 21 311 16 18 15 312 1 black line
vv5410 & vv6410 digital video interface format cd5410-6410f-3-0.fm commercial in confidence 40/105 figure 20 : cif field and frame formats - vp3 mode on, extra black lines off 17 blanking lines 319 2 black lines start of 2nd field line end of 2nd field line 7 blanking lines 292 visible lines 17 blanking lines 0 2nd field = 320 lines frame = 640 lines 1 0 2 3 9 10 11 301 299 300 12 302 319 303 2 black lines start of 1st field line end of 1st field line 7 blanking lines 292 visible lines 17 blanking lines 1st field = 320 lines 1 0 2 3 9 10 11 301 299 300 12 302 319 303 start of 1st field line 8 8
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 41/105 cd5410-6410f-3-0.fm figure 21 : cif field and frame formats - vp3 mode on, extra black lines on 17 black lines 319 8 black lines start of 2nd field line end of 2nd field line blanking line 292 visible lines 17 black lines 0 2nd field = 320 lines frame = 640 lines 1 0 2 3 9 10 11 301 299 300 12 302 319 303 8 black lines start of 1st field line end of 1st field line blanking line 292 visible lines 17 black lines 1st field = 320 lines 1 0 2 3 9 10 11 301 299 300 12 302 319 303 start of 1st field line 8 8
vv5410 & vv6410 digital video interface format cd5410-6410f-3-0.fm commercial in confidence 42/105 figure 22 : cif field and frame formats - vp3 mode off 319 16 black lines start of 2nd field line end of 2nd field line 0 2nd field = 320 lines frame = 640 lines 1 0 2 3 319 16 black lines start of 1st field line end of 2nd field line 10 dark lines 292 visible lines 1st field = 320 lines 1 0 2 3 17 18 30 28 29 26 317 319 318 start of 1st field line 16 16 27 10 dark lines 292 visible lines 17 18 317 318 end of 1st field line 30 28 29 26 27
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 43/105 cd5410-6410f-3-0.fm figure 23 : qcif field and frame formats - vp3 mode on, extra black lines off 0 frame = 320 lines start of 1st field line 2 black lines start of 1st field line end of 1st field line 7 blanking lines 148 visible lines blanking line 1st field = 160 lines 1 0 2 3 9 10 11 157 155 156 12 158 159 8 end of 2nd field line blanking line 158 159 2 black lines start of 2nd field line end of 2nd field line 7 blanking lines 148 visible lines blanking line 2nd field = 160 lines 1 0 2 3 9 10 11 157 155 156 12 158 159 8
vv5410 & vv6410 digital video interface format cd5410-6410f-3-0.fm commercial in confidence 44/105 figure 24 : qcif field and frame formats - vp3 mode on, extra black lines on 0 frame = 320 lines start of 1st field line 8 black lines start of 2nd field line end of 2nd field line blanking line 148 visible lines black line 2nd field = 160 lines 1 0 2 3 9 10 11 157 155 156 12 158 159 8 8 black lines start of 1st field line end of 1st field line blanking line 148 visible lines black line 1st field = 160 lines 1 0 2 3 9 10 11 157 155 156 12 158 159 8 end of 2nd field line black line 158 159
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 45/105 cd5410-6410f-3-0.fm 10 figure 25 : qcif field and frame formats - vp3 mode off 0 frame = 320 lines start of 1st field line 8 black lines start of 2nd field line end of 2nd field line 2 dark lines 148 visible lines 2nd field = 160 lines 1 0 2 3 9 11 157 155 156 12 159 8 8 black lines start of 1st field line end of 1st field line 2 dark lines 148 visible lines 1st field = 160 lines 1 0 2 3 9 10 11 157 155 156 12 159 8 end of 2nd field line 159 158 158
vv5410 & vv6410 digital video interface format cd5410-6410f-3-0.fm commercial in confidence 46/105 start of active video (sav) line figure 26 : line data format. end of active video (eav) video data y h d 1 d 0 d 3 d 2 p m p l p m p l p m p l p m p l p m p l p m p l number sav 8 h 0 h x h line code escape/sync sequence line code escape/sync sequence (i) (ii) (iii) (iv) (v) blanking line (bl) black line (bk) visible line (vl) start of frame (sof) end of frame (eof) p = blanking level (07 h ) p = valid black pixel data p = valid pixel data p = sensor status data, data at pixel position 0 and 1 set to blanking level, 07 h . p = blanking level (07 h ) n/2 even pixels n/2 odd pixels n pixels 0 1 n/2 -1 n/2 n -1 n -2 0 1 n -1 1 n-4 n-2 pixel number (unshuffled pixel data) pixel number (shuffled pixel data) 4-wire output mode line format 8-wire output mode ff h 00 h x h y h d 3 d 2 d 1 d 0 p p p p p p ff h 00 h 80 h ff h 0 h f h 0 h f h line period f h d 1 d 0 d 3 d 2 d 3 d 2 d 1 d 0 null chars pixel avg
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 47/105 cd5410-6410f-3-0.fm start of active video figure 27 : status line data format and fst signals end of active video serial interface register values 0 h 1 h 0 h 1 h 0 h 7 h f h f h 1 h 9 h (sav) (eav) c h 7 h 0 h 7 h 0 h 7 h a h 0 h 0 h 7 h 0 h 7 h 0 h 7 h 8 h 0 h 0 h 0 h start of frame line code devicel (register 1) padding characters ff h 00 h 80 h ff h 07 h 07 h 07 h 07 h 19 h 07 h a0 h 07 h 00 h c7 h 01 h 01 h ff h 8-wire output mode 4-wire output mode d 1 d 0 d 3 d 2 d 3 d 2 d 1 d 0 f h fst pin: 00 h 04 h 00 h 04 h 00 h 1c h 3f h 3f h 18 h 1c h 00 h 1c h 00 h 1c h 14 h 00 h 00 h 1c h 00 h 1c h 00 h 1c h 10 h 00 h 00 h line number 0 deviceh (register 0) devicel (register 1) 5-wire output mode d 1 d 0 d 3 d 2 3f h deviceh (register 0) line number 0 14 h 00 h padding characters padding characters 00 h (i) frame start pulse - qualifies status line information - selected by writing 2b01 to fg_mode register[7:6], see table 32 fo r details (ii) flash synchronisation mode for fst - high in line following eof, falls at start of eav in status line - selected by writin g 2b1x to serial register, 14(hex)
vv5410 & vv6410 digital video interface format cd5410-6410f-3-0.fm commercial in confidence 48/105 8.3.4 valid video line timing all valid video data is contained on active video lines. the pixel data appears as a continuous stream of bytes within the acti ve lines. the pixel data may be separated from the line header and end-of-line control sequence by a number of blank bytes (07 h ). 8.3.5 start of frame line timing the start of frame line which begins each video field contains no video data but instead contains the contents of the serial interface register map. immediately following the sav sequence there are 2 padding pixels, (see figure 27), output as blanking levels, (07 h ). there will be more blanking codes output after all the serial interface registers have been output . the padding pixels continue to be output until terminated by an end-of-line control sequence. to ensure that no escape/sync characters, (th e reserved ff,ff,00 sequence), appear in the sensor status/configuration information the code 07 h is output after each serial interface value. if a serial interface register location is unused then a default value, the deviceh register, is output. the read-out order of the registers is independent of whether the pixel read-out order is shuffled or un-shuffled. 8.3.6 end of frame line timing the end of frame line contains no video data. its sole purpose is to indicate the end of a frame. 8.4 detection of sensor using data bus state on power-up a sensor will pull all data lines high and these lines will remain high while the device is in the power up default , low power state. the device is removed from this low power mode by the i2c host writing to sensor register, setup0 [address 10 16 ]. when the device exits the low power mode it will follow a defined power up sequence, please see figure 30 for more details. upon completion of the power up sequence the sensor will begin streaming video. 8.5 resetting the sensor via the serial interface bit 2 of setup0 register allows the vv5500/vv6500 sensor to be reset to its power-on state via the serial interface. setting th is soft reset bit causes all of the serial interface registers including the soft reset bit to be reset to their default value s. this soft reset leaves the sensor in low-power mode. 8.6 resetting the sensor via the resetb pin on power-up the resetb pin is configured as an active low system reset which has the same effect as a soft reset issued via the serial interface as described above. 8.7 resynchronising the sensor via the resetb pin con?gured as sinb bit 5 of the pin mapping register [21] allows the resetb pin to be re-configured as an active low (edge triggered) system synchronisation signal which will reset the video timing to the beginning of a field but will not reset the serial registers therefore the host does not have to reconfigure the sensor following a resynchronisation.
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 49/105 cd5410-6410f-3-0.fm figure 28 : reseting the sensor via the serial interface (example shown is 4wire output mode) f h 9 h ,6 h ,9 h ,6 h ... n 0 1 d[3:0] clki frame number sda scl 2 3 4 5 start of frame line for the 1st frame of valid video data. valid video data. sr0 sr1 sr2 sr6 sr7 setup0[2] sr0-sr1 soft-reset command. at the end of the command the sensor is reset and enters low-power mode. sr2 the sensor enters low-power mode. sr3-sr4 exit low power mode command. powers-up analogue circuits and initates the sensors 4-frame start-up sequence sr5-sr6 1 frame of alternating 9 h & 6 h data on d[3:0] for the host to determine the best sampling phase for the nibble data (d[3:0]). sr7-sr8 4 frames after the exit low-power mode command, the sensor starts outputing valid video data. one frame of 9 h &6 h data. f h sr3 sr4 sr5 sr8 setup0[0]
vv5410 & vv6410 digital video interface format cd5410-6410f-3-0.fm commercial in confidence 50/105 8.8 power-up, low-power and sleep modes please note that the following descriptions of low power and sleep modes assumes that the user has selected the optional 4 wire output mode, that is d[3:0] will transmit the digital video data. if the 5-wire or 8-wire modes are selected the same basic behaviour is followed however the contents of the data bus will differ slightly. 8.8.1 power-up/down (figure 29) the sensor enters low-power mode on power-up. on power-up all of the data bus lines are driven high immediately and the device is in low-power mode (section 8.8.2). the sensor will remain in the low power mode until the external host sends the appropriate message over i2c to clear the low power bit - bit0 of serial reguister, setup0, index 10 16 . after the exit low-power mode command has been sent the sensor will output for one frame, a continuous stream of alternating 9 h and 6 h values on d[3:0] the patterns generated in 5 and 8 wire modes are given in table 16 below. by locking onto the resulting 0101/1010 patterns appearing on the data bus lines the host can determine the best sampling position for the nibble data. after the last 9 h 6 h pair has been output the data bus returns to f h ,(1f h in 5 wire mode), until the start of fifth frame. at this point the first active video frame will be output. after the host has determined the correct sampling position for the data, it should then wait for the next start of frame line (sof). pu0 system power up pu1 sensor enters low power mode and databus bits driven high. pu2 host enables the sensor clock, clki. pu3-pu4 the host sends a soft-reset command to the sensor via the serial interface. this ensures that the sensor is in low-power mode. pu5 host issues command to remove sensor from low-power mode. pu6-pu7 sensors begins execution 4 frame start sequence. pu8-pu9 one frame of alternating 9 h & 6 h data on d[3:0] for the host to determine the best sampling phase for video data. pu10-pu11 4 frames after the exit low-power mode serial comms, the sensor starts outputing valid video data. table 15 : typical system power-up
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 51/105 cd5410-6410f-3-0.fm figure 29 : typical system power-up procedure 4 3 2 1 0 f h f h 3v3 0v 9 h ,6 h ,9 h ,6 h ... regulated sensor power d[3:0] clki frame number sda scl pu0 pu1 pu2 pu3 pu4 pu5 start of frame line for the 1st frame of valid video data. one frame of 9 h & 6 h data. pu6 pu7 pu8 pu9 pu10 pu11 setup0[2] setup0[0]
vv5410 & vv6410 digital video interface format cd5410-6410f-3-0.fm commercial in confidence 52/105 8.8.2 low-power mode (figure 30) under the control of the serial interface the sensor analog circuitry can be powered down and then repowered. when the low- power bit is set via the serial interface, all the data bus lines will go high at the end of the end of frame line of the curre nt frame. at this point the analog circuits in the sensor will power down. the system clock must remain active for the duration of low power mode. during low power mode only the analog circuits are powered down, the values of the serial interface registers e.g. exposure and gain are preserved. the internal frame timing is reset to the start of a video frame on exiting low-power mode. in a similar manner to the previous section, the first frame after the serial comms contains a continuous stream of alternating 9 h and 6 h - or equivalent for the alternative ouput databus widths - to allow the host to re-confirm its sampling position. then three frames later the first start of frame line is generated. 8.8.3 sleep mode sleep mode is similar to the low-power mode, except that analog circuitry remains powered. when the sleep command is received via the serial interface the pixel array will be put into reset and the data lines all will go high at the end of the current frame. again the system clock must remain active for the duration of sleep mode. when sleep mode is disabled, the cmos sensors frame timing is reset to the start of a frame. during the first frame after exiting from sleep mode the data bus will remain high, while the exposure value propagates through the pixel array. at the start of the second frame the first start of field line will be generated. 8.8.4 system clock status during sensor low-power modes to allow the sensor to enter and exit the low power and sleep modes the system clock, clki, must be active. 8.9 suspend mode under the control of the suspend pin vv5410/vv6410 can be forced into an ultra low power mode. the sensor will consume less than 80ua of current while suspended. while the sensor is in this mode video output is turned off and no serial communications can occur. the suspend mode is effectively identical to a power on reset - all the video timing blocks within the sensor are reset as are the contents of the serial interface, therefore the user will have to perform a compete reconfiguration of the device on exitting suspend. the sensor will also repeat the full 4 field power up sequence. 8.10 data quali?cation clock, qck vv5410/vv6410 provides a data qualification clock, (see figure 31), to qualify the information output on data bus. the sensor can generate two styles of qualification clock: ? fast qck, clocks at nibble rate. the falling edge of this clock qualifies data mode 10-bit value output data bus pattern 4-wire 258 h 9 h /6 h (1001 2 /0110 2 ) 5-wire 136 h 09 h /16 h (01001 2 /10110 2 ) 8-wire 096 h / 069h 25 h /1a h (00100101 2 /00011010 2 ) table 16 : output data bus patterns for determination of best sampling position mode description approx. sensor current suspend sensor in lowest power state. suspend has been asserted by host. c.80ua table 17 : vv5410/vv6410 suspend mode power consumption
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 53/105 cd5410-6410f-3-0.fm . figure 30 : entering and exiting low power mode (example is 4wire mode). n 0 1 d[3:0] clki frame number sda scl 2 3 4 5 start of frame line for the 1st frame of valid video data. valid video data. lp0 lp1 lp3 lp2 lp7 lp8 setup0[0] lp0-lp1 enter low power mode command. lp2 at end of current frame, the sensor will enter the low power mode and the databus will be driven high. lp3-lp4 exit low power mode command sent to sensor - sensor begins power up sequence. lp5-lp6 1 frame of alternating 9 h & 6 h data on d[3:0] for the host to determine the best sampling phase for the nibble data (d[3:0]). lp7-lp8 4 frames after the exit low power mode command, the sensor starts outputing valid video data. one frame of 9 h &6 h data. f h f h 9 h ,6 h ,9 h ,6 h ... lp4 lp5 lp6
vv5410 & vv6410 digital video interface format cd5410-6410f-3-0.fm commercial in confidence 54/105 ? the slow qck, clocks at pixel rate. both the falling and rising edge of this clock are used to qualify data. the most significant data nibble is qualified by the rising edge of the slow qck and the least significant nibble is qualified by the falling edge o f the slow qck. there are 4 modes of operation of qck. 1. disabled (always low - default mode of operation) 2. free running - quali?es the entire output data stream. 3. qualify embedded control sequences, status data, (from the sof line), and pixel data. 4. qualify pixel data only, (this will include data from the black lines). the operating mode for qck is set via the serial interface. the qck output can be tri-stated either when oeb is driven high or via the appropriate control bit in the serial interface, (see data_format register[22]). the qck pin can also be configured to output the state of a serial interface register bit. this feature allows the sensor to co ntrol external devices, e.g. stepper motors, shutter mechanisms. full details of how to configure the qck output pin can be found in 2 registers, fg_mode[20] and pin_mapping[21].
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 55/105 cd5410-6410f-3-0.fm end of active video (eav) start of active video (sav) pixel data figure 31 : quali?cation of output data (border rows and columns enabled). video data f h line format 4-wire nibble output mode - d[3:0] d 1 d 0 f h f h f h p m p l p m p l p m p l p m p l crystal clock or external clock applied to cki slow quali?cation clock, qck (i) free running (ii) control sequences and pixel data (iii) pixel data only p m = pixel value - most significant nibble, p l = pixel value - least significant nibble, p = 8-bit pixel value fast quali?cation clock, qck (i) free running (ii) control sequences and pixel data (iii) pixel data only
vv5410 & vv6410 digital video interface format cd5410-6410f-3-0.fm commercial in confidence 56/105 figure 32 : frame/field level timings for fst and lst. start of field black lines blanking lines visible lines end of field blanking lines blanking lines start of field 2nd field 1 frame start of field black lines blanking lines visible lines end of field blanking lines 1st field frame/field format: lst: (iii) data only (ii) control plus data (i) free running (ii) shutter mode fst pin: (i) fst
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 57/105 cd5410-6410f-3-0.fm 8.10.5 line start signal, lst there are 4 modes of operation for the lst pin programmable via the serial interface, (see fg_mode[20]): 1. disabled (always low- default). 2. free running - lst signal occurs once at the beginning of every line. 3. all lines except blanking lines are quali?ed by lst. 4. only black and visible lines are quali?ed by lst. the lst is tri-stated either when oeb is driven high or via the appropriate control bit in the serial interface, (see data_form at register[22]). table 18below details the lst timing for the different video modes, (see figure 33 for specification of t1 and t 2). 8.10.6 frame start signal, fst there are 3 modes of operation for the fst pin programmable via the serial interface: 1. disabled (always low- default). 2. frame start signal. the fst signal occurs once frame, is high for 356 pixel periods (712 system clock periods) and quali?es the data in the start of frame line. 3. shutter/electronic flash synchronisation signal - fst rises a the start of the video data in the ?rst black/blank line after the eof line and falls at the end of data in the sof line. the fst output is tri-stated either when oeb is driven high or via the appropriate control bit in the serial interface, (see data_format register[22]). the configuration details for fst can be found in fg_mode register[20]. video mode t1 t2 pcks us pcks us cif 21 5.25 16 4.000 qcif (both pan tilt and sub sampled, 16mhz clock) 6 6.00 15 15.00 qcif (both pan tilt and sub sampled, 8mhz clock) 6 6.00 15 15.00 pal 33 4.652 42 5.962 ntsc 27 4.714 12 2.095 table 18 : lst timing
vv5410 & vv6410 digital video interface format cd5410-6410f-3-0.fm commercial in confidence 58/105 figure 33 : line level timings for fst and lst. video data start of active video (sav) eav inter-line period (databus = f h ) end of active video (eav) fst pin: frame start pulse - qualifies status line information end of active video (eav) lst pin: 6 pixels 180/306/356 pixels 6 pixels 1 line t1 t2 video data
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 59/105 cd5410-6410f-3-0.fm figure 34 : frame/field level timings for fst and qck. start of field black lines blanking lines visible lines end of field blanking lines blanking lines start of field 2nd field 1 frame start of field black lines blanking lines visible lines end of field blanking lines 1st field frame/field format: qck: (iii) data only (ii) control plus data (i) free running (ii) shutter mode fst pin: (i) fst
vv5410 & vv6410 serial control bus cd5410-6410f-3-0.fm commercial in confidence 60/105 9. serial control bus 9.1 general description writing configuration information to the video sensor and reading both sensor status and configuration information back from the sensor is performed via the 2-wire serial interface. communication using the serial bus centres around a number of registers internal to the video sensor. these registers store sensor status, set-up, exposure and system information. most of the registers are read/write allowing the receiving equipment to change their contents. others (such as the chip id) are read only. the main features of the serial interface include: ? variable length read/write messages. ? indexed addressing of information source or destination within the sensor. ? automatic update of the index after a read or write message. ? message abort with negative acknowledge from the master. ? byte oriented messages. the contents of all internal registers accessible via the serial control bus are encapsulated in each start-of-field line - see section 8.3.5. 9.2 serial communication protocol the co- processor or host must perform the role of a communications master and the camera acts as either a slave receiver or transmitter.the communication from host to camera takes the form of 8-bit data with a maximum serial clock host frequency of up to 100 khz. since the serial clock is generated by the bus master it determines the data transfer rate. data transfer protocol on the bus is illustrated in figure 35. 9.3 data format information is packed in 8-bit packets (bytes) always followed by an acknowledge bit. the internal data is produced by sampling sda at a rising edge of scl . the external data must be stable during the high period of scl . the exceptions to this are start (s) or stop (p) conditions when sda falls or rises respectively, while scl is high. a message contains at least two bytes preceded by a start condition and followed by either a stop or repeated start, (sr) followed by another message. the first byte contains the device address byte which includes the data direction read, (r) , ~write , (~w), bit. the lsb of the address byte indicates the direction of the message. if the lsb is set high then the master will read data from the slave and if the lsb is reset low then the master will write data to the slave. after the r, ~w bit is sampled, the data direction cannot be changed, until the next address byte with a new r, ~w bit is received. 12 7 8 a start condition stop condition sda scl acknowledge p s 3 4 56 address or data byte msb lsb figure 35 : serial interface data transfer protocol
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 61/105 cd5410-6410f-3-0.fm the byte following the address byte contains the address of the first data byte (also referred to as the index ). the serial interface can address up to 128, byte registers. if the msb of the second byte is set the automatic increment feature of the address index is selected. 9.4 message interpretation all serial interface communications with the sensor must begin with a start condition. if the start condition is followed by a valid address byte then further communications can take place. the sensor will acknowledge the receipt of a valid address by driving the sda wire low. the state of the read/~write bit (lsb of the address byte) is stored and the next byte of data, sampled from sda, can be interpreted. during a write sequence the second byte received is an address index and is used to point to one of the internal registers. the msbit of the following byte is the index auto increment flag. if this flag is set then the serial interface will automatically increment the index address by one location after each slave acknowledge. the master can therefore send data bytes continuously to the slave until the slave fails to provide an acknowledge or the master terminates the write communication with a stop condition or sends a repeated start , (sr) . if the auto increment feature is used the master does not have to send indexes to accompany the data bytes. as data is received by the slave it is written bit by bit to a serial/parallel register. after each data byte has been received by the slave, an acknowledge is generated, the data is then stored in the internal register addressed by the current index. during a read message, the current index is read out in the byte following the device address byte. the next byte read from the slave device are the contents of the register addressed by the current index. the contents of this register are then parallel loaded into the serial/parallel register and clocked out of the device by scl. at the end of each byte, in both read and write message sequences, an acknowledge is issued by the receiving device. although vv5410/vv6410 is always considered to be a slave device, it acts as a transmitter when the bus master requests a read from the sensor. at the end of a sequence of incremental reads or writes, the terminal index value in the register will be one greater the last location read from or written to. a subsequent read will use this index to begin retrieving data from the internal registers. a message can only be terminated by the bus master, either by issuing a stop condition, a repeated start condition or by a negative acknowledge after reading a complete byte during a read operation. 9.5 the programmers model there may be up to 128, 8-bit registers within the camera, accessible by the user via the serial interface. they are grouped 0 0 1 0 0 0 0 figure 36 : vv5410/vv6410s serial interface address r/w s address[7:1] r / w bit a data[7:0] a sensor acknowledges valid address acknowledge from slave index[6:0] inc p a a data[7:0] [0] address auto increment index bit figure 37 : serial interface data format
vv5410 & vv6410 serial control bus cd5410-6410f-3-0.fm commercial in confidence 62/105 according to function with each group occupying a 16-byte page of the location address space. there may be up to eight such groups, although this scheme is purely a conceptual feature and not related to the actual hardware implementation, the primary categories are given below: ? status registers (read only). ? setup registers with bit significant functions. ? exposure parameters that influence output image brightness. ? system functions and analog test bit significant registers. any internal register that can be written to can also be read from. there are a number of read only registers that contain devi ce status information, (e.g. design revision details). names that end with h or l denote the most or least significant part of the internal register. note that unused locations in th e h byte are packed with zeroes. stmicroelectronics sensors that include a 2-wire serial interface are designed with a common address space. if a register parameter is unused in a design, but has been allocated an address in the generic design model, the location is referred to as reserved . if the user attempts to read from any of these reserved or unused locations a default byte will be read back. in vv5410/vv6410 this data is 19 h . a write instruction to a reserved (but unused) location is illegal and would not be successful as the device would not allocate an internal register to the data word contained in the instruction. a detailed description of each register follows. the address indexes are shown as decimal numbers in brackets [....] and are expressed in decimal and hexadecimal respectively. index 10 index 16 name length r/w default comments status registers - [0-15] 0 0 deviceh 8 ro 0001_1001 2 chip identification number including revision indicator 1 1 devicel 8 ro 1010_0000 2 2 2 status0 8 ro 0001_0000 2 user can determine whether timed serial interface data has been consumed by interrogating flag states 3 3 line_counth 8 ro n/a current line counter value 4 4 line_countl 8 ro n/a 5 5 xendh 1 ro 359 end x coordinate of image size 6 6 xendl 8 ro 7 7 yendh 1 ro 293 end y coordinate of image size 8 8 yendl 8 ro 9 9 dark_avgh 4 ro 0 this is the average pixel value returned from the dark line offset cancellation algorithm (2s complement notation) 10 a dark_avgl 8 ro 0 11 b black_avgh 4 ro 0 this is the average pixel value returned from the black line offset cancellation algorithm (2s complement notation) 12 c black_avgl 8 ro 0 13 d status1 2 ro 00 flags to indicate whether the x or y image coordinates have been clipped 14-15 e-f unused setup registers - [16-31] table 19 : serial interface address map.
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 63/105 cd5410-6410f-3-0.fm 16 10 setup0 8 r/w 0000_1001 2 low-power/sleep modes & video timing 17 11 setup1 8 r/w 1100_0000 2 various parameters 18 12 sync_value 8 r/w 0001_1111 2 contains pixel counter reset value used by external sync 19 13 reserved 20 14 fg_modes 8 r/w 0000_0000 2 frame grabbing modes (fst, lst and qck) 21 15 pin_mapping 7 r/w 000_1000 2 fst and qck mapping modes. 22 16 data_format 8 r/w 0000_0001 2 data resolution 23 17 op_format 7 r/w 001_1000 2 output coding formats 24 18 mode_select 2 r/w 01 2 various mode select bits 25 - 31 19-1f unused exposure registers - [32-47] 32 20 fineh 2 r/w 0 fine exposure. 33 21 finel 8 r/w 34 22 coarseh 2 r/w 302 coarse exposure 35 23 coarsel 8 r/w 36 24 analog gain 8 r/w 1111_0000 analog gain setting 37 25 clk_div 4 r/w 0 clock division 38-43 26-2b reserved 44 2c dark offseth 3 r/w 0 dark line offset cancellation value (2s complement notation) 45 2d dark offsetl 8 r/w 46 2e dark offset setup 7 r/w 0110 0001 2 dark line offset cancellation enable 47 2f reserved colour registers - [48-79] 48 - 79 30-4f reserved 8 r/w video timing registers - [80-103] 80-81 50-51 reserved 82 52 line_lengthh 2 r/w 415 line length (pixel clocks) 83 53 line_lengthl 8 r/w 84 - 86 54-56 reserved 87 57 x-offseth 1 r/w 5 x-co-ordinate of top left corner of region of interest (x-offset) 88 58 x-offsetl 8 r/w 89 59 y-offseth 1 r/w 3 y-co-ordinate of top left corner of region of interest (y-offset) 90 5a y-offsetl 8 r/w 91 - 96 5b-60 reserved 97 61 field_lengthh 2 r/w 319 field length (lines) 98 62 field_lengthl 8 r/w 99-102 63-66 reserved 103 67 unused r/w text overlay registers - [104-107] 104 - 105 68-69 reserved 106 - 107 6a-6b unused index 10 index 16 name length r/w default comments table 19 : serial interface address map.
vv5410 & vv6410 serial control bus cd5410-6410f-3-0.fm commercial in confidence 64/105 9.5.1 status registers - [0 - 15], [0-f] [0-1], [0-1] - deviceh and devicel these registers provide read only information that identifies the sensor type that has been coded as a 12bit number and a 4bit mask set revision identifier. the device identification number for vv5410/vv6410 is 410 i.e. 0001 1001 1010 2 . the initial mask revision identifier is 0 i.e. 0000 2 . [2] ,[2] - status0 serial interface autoload registers - [108-111] 108 - 109 6c-6d reserved 110 - 111 6e-6f unused system registers - [112-127] 112 70 black offseth 3 r/w - 64 black offset cancellation default value (2s complement notation) 113 71 black offsetl 8 r/w 114 72 black offset setup 6 r/w 0011 0001 2 black offset cancellation setup 115 73 unused 116 74 reserved 117 75 cr0 8 r/w 0000 0000 2 analog control register 0 118 76 cr1 8 r/w 0000 0000 2 analog control register 1 119 77 as0 8 r/w 0101 1010 2 adc setup register 120 78 at0 8 r/w 0000 0000 2 analog test register 121 79 at1 8 r/w 0000 0001 2 audio amplifier setup register 122 - 125 7a-7d unused 126 7e reserved 127 7f reserved bits function default comment 7:0 device type identifier 0001 1001 2 most significant 8 bits of the 12 bit code identifying the chip type. table 20 : [0], [0] - deviceh bits function default comment 7:4 device type identifier 1010 2 least significant 4 bits of the 12 bit code identifying the chip type. 3:0 mask set revision identifier 0000 2 table 21 : [1] ,[1] - devicel bit function default comment 0 fine exposure value update pending 0 fine exposure value sent but not yet consumed by the sensor table 22 : [2], [2] - status0 index 10 index 16 name length r/w default comments table 19 : serial interface address map.
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 65/105 cd5410-6410f-3-0.fm [3-4], [3-4] - line_counth & line_countl [5-6], [5-6] - xendh & xendl [7-8], [7-8] - yendh & yendl 1 coarse exposure value update pending 0 coarse exposure value sent but not yet consumed by the sensor 2 gain value update pending 0 gain value sent but not yet consumed by the sensor 3 clock division update pending 0 clock divisor sent but not yet consumed by the sensor 4 odd/even frame 1 the flag will toggle state on alternate frames 5 pan image parameters pending 0 pan image parameters sent but not yet consumed by the sensor 6 tilt image parameters pending 0 tilt image parameters sent but not yet consumed by the sensor 7 video timing parameter update pending flag 0 video timing parameters sent but not yet consumed by sensor register index bits function default comment 3 0 current line count msb - displays current line count 4 7:0 current line count lsb - table 23 : [3-4], [3-4] - current line counter value. register index bits function default comment 5 0 xend msbs 359 these registers contain the end x coordinate of the read out image size, (the x offset register contains the start x coordinate) 6 7:0 xend ls byte table 24 : [5-6], [5-6] - xend register index bits function default comment 5 0 yend ms bits 293 these registers contain the end y coordinate of the read out image size, (the y offset register contains the start y coordinate) 6 7:0 yend ls byte table 25 : [7-8], [7-8] - yend bit function default comment table 22 : [2], [2] - status0
vv5410 & vv6410 serial control bus cd5410-6410f-3-0.fm commercial in confidence 66/105 [9-12], [9-c] - black_avg & dark_avg [13], [d] - status1 register [14-15], [e-f] - unused 9.5.2 setup registers - [16 - 31] ,[10-1f] [16] ,[10] - setup0 [ register index bits function default comment 9 3:0 dark avg ms bits 0 the calculated pixel average over a series of dark lines (1,2 or 4 lines). the pixel sample size from each dark line will be image size dependent up to a maximum of 256 the average value is a signed 12 bit number 10 7:0 dark avg ls byte 0 11 3:0 black avg ms bits 0 the calculated pixel average over a series of black lines (4 or 8 lines). the pixel sample size from each black line will be image size dependent up to a maximum of 256 the average value is a signed 12 bit number 12 7:0 black avg ls byte 0 table 26 : [9-12], [9-c] - black & dark averages bit function default comment 0 x image parameters clipped 0 if this bit is set then the current x offset parameter requested has caused the x coordinates to be clipped 1 y image parameters clipped 0 if this bit is set then the current y offset parameter requested has caused the y coordinates to be clipped 7:2 unused 000000 table 27 : [13], [d] - status1 bit function default comment 0 low power mode: off / on 1 powers down the sensor array. the output data bus goes to f h . on power-up the sensor enters low power mode. 1 sleep mode: off / on 0 puts the sensor array into reset. the output data bus goes to f h . table 28 : [16], [10] - setup0
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 67/105 cd5410-6410f-3-0.fm [17], [11] - setup1 2 soft reset off / on 0 setting this bit resets the sensor to its power-up defaults. this bit is also reset. 3 frame/field rate select: 25 fps (pal) / 30 fps (ntsc) 1 5:4 reserved 00 7:6 video timing mode select 00 00 - cif timing modes 01 - pal/ntsc 3.2 fsc timing modes 10 - pan/tilt/qcif timing modes if this mode is selected a qcif size image will be output. the coordinates which de?ne the top left corner of the qcif portion of the array to be output are de?ned by the parameters in registers 88 - 91 inclusive. by default the x- and y-sizes of the output image are180 & 148 respectively. 11 - sub-sampled qcif timing modes if this mode is selected a qcif size image will be output. the cif image is sub-sampled in groups of 4 to preserve the bayer pattern with every second group of pixels & lines skipped. video mode setup0 [7:6] setup0 [3] system clock divisor video data line length field length data format (default) comment 1000 4 356 x 292 500 320 5-wire cif 25fps 21 4 356 x 292 416 320 5-wire cif 30fps 3010 2 356 x 292 454 312/313 5-wire pal (3.2 fsc) 41 2 306 x 244 364 262/263 5-wire ntsc (3.2 fsc) 5100 8 180 x 148 250 160 5-wire pan/tilt qcif 25fps 61 8 180 x 148 208 160 5-wire pan/tilt qcif 30fps 7110 8 180 x 148 250 160 5-wire sub-sampled qcif 25fps 81 8 180 x 148 208 160 5-wire sub-sampled qcif 30fps table 29 : video timing modes bit function default comment 2:0 reserved 000 3 enable immediate clock division update. off /on 0 allow manual change to clock division to be applied immediately 4 enable immediate gain update. off /on 0 allow manual change to gain to be applied immediately table 30 : [17], [11] - setup1 bit function default comment table 28 : [16], [10] - setup0
vv5410 & vv6410 serial control bus cd5410-6410f-3-0.fm commercial in confidence 68/105 [18], [12] - sync_reset [19], [13] - reserved [20], [14] - fg_modes bits [3:2] of the fg_mode register are mode dependent. if the ntsc or pal video modes are selected then the free running qck mode will be selected. the slow qck is selected by default, regardless of the video mode. note1: the fst pin will always output the free running version of qck (either inverted or normal) 5 enable additional black lines (lines 3-8) off /on 0 if enabled this bit will also enable the lines immediately following the end of frame line. this bit can only set/reset if the vp3 mode (on) has been selected. in vp3 mode (off) operation all possible black lines are always output. 6 reserved 1 7 pixel read-out order (hshuffle) unshuffled or shuffled 1 it is strongly recommended to use shuffled horizontal read-out with vv6410 sensor. bit function default comment 7:0 pixel counter reset value 31 during synchronisation the pixel counter can be reset to the known value or offset by up to 255 pcks into the pixel count sequence. table 31 : [18], [12] - sync_reset bit function default comment 1:0 fst/qck pin modes 00 selection of fst, qck pin data 3:2 qck modes 00 00 - if cif & qcif mode selected 01 - if ntsc and pal mode selected 5:4 lst modes 00 see table 35 below for details 7:6 fst modes 00 see table 36 below for details table 32 : [20], [14] - fg_modes fg_mode[1:0] fst pin qck pin 0 0 fst slow qck 0 1 fst fast qck 1 0 fast qck note1 slow qck 1 1 invert of fast qck note1 fast qck table 33 : fst/qck pin selection bit function default comment table 30 : [17], [11] - setup1
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 69/105 cd5410-6410f-3-0.fm . the option to enable the qclk during the data and control period of the line must not be selected if monochrome (shuffled or unshuffled) video has been selected. [21], [15] - pin_mapping fg_mode[3:2] qck state 0 0 off 0 1 free running 1 0 valid during data and control period of line 1 1 valid only during data period of line table 34 : qck modes fg_mode[5:4] lst pin 0 0 off 0 1 free running 1 0 output for black, video data and status lines 1 1 output only for black and video data lines. table 35 : lst modes fg_mode[7:6] fst pin 0 0 off 0 1 normal behaviour, fst will qualify the visible pixels in the status line 1 x special digital stills mode. fst will be asserted at the beginning of valid data on the line following the eof line. fst will be cleared at the end of the visible pix- els in the following status line. table 36 : fst modes bit function default comment 0 map serial interface register bits values on to the qck and fst pins off /on 0 1 serial interface bit for qck pin 0 2 serial interface bit for fst pin 0 4:3 output driver strength select 00 default setting selects 2ma driver table 37 : [21], [15] - pin_mapping
vv5410 & vv6410 serial control bus cd5410-6410f-3-0.fm commercial in confidence 70/105 [22], [16] - data_format 5 enable resetb pin as sin off / on 0 on power up the resetb pin is con?gured as an active low system reset which will synchronise the video timing logic and reset all serial registers to their default state. setting this bit con?gures the resetb pin as an active high system synchronisation signal (sin) which will synchronise the video timing but will not reset the serial registers. 7:6 unused 0 mapping enable fst pin qck pin 0 fst qck 1 pin_mapping[2] pin_mapping[1] table 38 : fst/qck pin selection oeb_composite pin_map[4] pin_map[3] comments 0 0 0 drive strength = 2ma (default) 0 0 1 drive strength = 4ma 0 1 0 drive strength = 6ma 0 1 1 unallocated 1 x x outputs are not being driven therefore driver strength is irrelevant table 39 : output driver strength selection bit function default comment 1:0 unused 1 2 line read-out order (vertical) unshuffled or shuffled 0 if the line read out is shuffled then all the even address rows will be read out first followed by all the odd address rows 3 pixel read-out order (hmirror) normal or mirrored 0 if the pixel read out is horizontally mirrored then the columns are read out in reverse order, that is the column on the right of the sensor array will appear on the left of the displayed image and vice versa 4 line read-out order (vertical flip) normal or mirrored 0 if the line read out is vertically mirrored then the rows are read out in reverse order, that is the row at the bottom of the array will appear at the top of the displayed image and vice versa. table 40 : [22], [16] - data_format bit function default comment table 37 : [21], [15] - pin_mapping
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 71/105 cd5410-6410f-3-0.fm 5 fst/lst enable /tri-state 0 the fst/lst digital outputs can be tri-stated but are enabled as outputs by default. the enabling/disabling of fst/lst can be retimed to a ?eld boundary. the state of this control bit is always available via a serial interface read, i.e. it does not have to wait to change state at a ?eld boundary 6 qck enable /tri-state 0 the qck output can be tri-stated independently. the enabling/disabling of qck can be retimed to a ?eld boundary. the state of this control bit is always availa- ble via a serial interface read, i.e. it does not have to wait to change state at a ?eld boundary. 7 pre clock generator divide on/ off 0 the cif and qcif video modes expect a recom- mended set of input clock frequencies, however the acceptable range of clock frequencies can be extended if this bit is set. if this bit is set then the primary input clock will be divided down by 1.5 prior to the clock gen- erator, thus if the expected clock input is 16 mhz, we can set this bit and accept 24 mhz and achieve the same ?nal frame rate. oeb pin data_format[5] oeb_composite comments 0 0 0 fst/lst outputs enabled. 0 1 1 fst/lst outputs are tri-stated by data_format[5] 1 0 1 fst/lst outputs are tri-stated by oeb pin. 1 1 1 fst/lst outputs are tri-stated. table 41 : fst/lst output control oeb pin data_format[6] oeb_composite comments 0 0 0 qck output enabled. 0 1 1 qck output is tri-stated by op_format[6] 1 0 1 qck output is tri-stated by oeb pin. 1 1 1 qck output is tri-stated. table 42 : qck output control bit function default comment table 40 : [22], [16] - data_format
vv5410 & vv6410 serial control bus cd5410-6410f-3-0.fm commercial in confidence 72/105 [23], [17] - op_format note: oeb_composite is the logical or of op_format[5] and the oeb pin. [24], [18] - mode_select this register allows the user to configure the sensor to operate with the present generation of coprocessors as well as anticipated future devices. bit function default comment 1:0 data format select. 0 00 - 5 wire parallel output 01 - 4 wire parallel output 1x - 8 wire parallel output note: if the 8 wire output option has been selected then the fst and lst pins will output data bits 5 and 6 respectively, normal fst and lst function is not available 2 embedded sav/eav escape sequences 1 on / off 1. please note that if the embedded coding sequences are disabled then the fst signal is also disabled. the qck output will continue to function if the free running option has been selected. the lst functionality is unaffected by the state of this bit. 0 0 - insert embedded control sequences e.g start and end of active video into output video data 1 - pass-through mode. output video data equals adc data. 4:3 reserved 11 5 tri-state output data bus enabled / tri-state 0 on power up the data bus pads are enabled by default. this bit is ored with the oeb pin to generate the enable signal for the data pins as detailed in table 44 6 re-time tri-state update. off / on 0 re-time new tri-state value to a field boundary. this bit affects the updating of the op_format[5] as well as data_format[6:5] 7 unused 0 table 43 : [23], [17] - op_format oeb pin op_format[5] oeb_composite comments 0 0 0 data outputs enabled. 0 1 1 data outputs are tri-stated by op_format[5] 1 0 1 data outputs are tri-stated by oeb pin. 1 1 1 data outputs are tri-stated. table 44 : data bus output control bit function default comment 0 coprocessor device is vp3 no/ yes 1 by default the sensor expects the coprocessor to be a vp3 device. if the sensor is not being used with a vp3 device then this bit should be reset. this bit controls the arrangement of black/dark/visible lines within the ?eld. it does not alter timing. please see table 45 : [24], [18] - mode select
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 73/105 cd5410-6410f-3-0.fm [25-31], [19-1f] - unused 9.5.3 exposure control registers [32 - 47], [20-2f] there is a set of programmable registers which controls the sensitivity of the sensor. the registers are as follows: 1. fine exposure. 2. coarse exposure. 3. analog gain. 4. clock division note : as we know from an explanation earlier in this document (see section 6. for further details) the exposure control registers are not updated immediately, rather they are timed to be updated at a precise point in the field timing. the range of some parameter values is limited and any value programmed out-with this range will be clipped to the maximum currently permitted, (the fine and coarse maximum allowable settings are set by the current line and field length respectively) . 1 retro mode for gain application off /on 0 the gain passed to the cab comprises 2 components, idac[3:0] and cdac[5:0]. if the user selects the retro mode then the idac value will be the inverse of the ls gain nibble. the user is barred from writing to the ms gain nibble. in the non retro mode all 8 bits are availa- ble to program. the 2 ls bits of cdac[5:0] are ?xed at 2b11. 2 select log cdac ramp off /on 0 by default the same cdac value is applied for the duration of every line of every ?eld. setting this bit causes the cdac value to be varied during the line. 7:3 index 10 index 16 bits function default comment 32 20 0 fine msb exposure value 0 the maximum fine exposure is line length dependent. the expressions used to calculate the maximum fine exposure for each of the default video modes, that can be selected via setup0 register, are as follows ntsc = line length - 51 pal = line length - 86 cif = line length - 51 qcif = line length - 23 33 21 7:0 fine lsb exposure value bit function default comment table 45 : [24], [18] - mode select
vv5410 & vv6410 serial control bus cd5410-6410f-3-0.fm commercial in confidence 74/105 table 46 : exposure related registers 34 22 0 coarse msb exposure value 302 the maximum allowable coarse exposure setting is filed length dependent. we provide the maximum coarse exposure settings for each of the standard video modes. ntsc = 260 pal = 310 cif (25 & 30 fps) = 318 qcif (25 & 30 fps) = 158 35 23 7:0 coarse lsb exposure value 36 24 7:0 analog gain value 1111_0000 bits [7:4] cdac gain control cdac default = 63 (10-bit modes) cdac default = 31 (9-bit modes) bits[3:0] idac maximum recommended idac value = 12. 37 25 3:0 clock divisor value 0 the user can opt to slow the internal clocks down form their default settings. table 47 describes the range of clock divisors that may be selected. clock divisor setting pixel clock divisor 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 10 1010 11 1011 12 1100 13 1101 14 1110 15 table 47 : clock divisor values index 10 index 16 bits function default comment
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 75/105 cd5410-6410f-3-0.fm 1111 16 clock divisor setting pixel clock divisor table 47 : clock divisor values
vv5410 & vv6410 serial control bus cd5410-6410f-3-0.fm commercial in confidence 76/105 [38-43], [26-3b] - reserved [44 - 45], [3c-3d] - dark pixel offset [46], [3e] - dark pixel cancellation setup register [47], [3f] - reserved [48-79], [30-4f] - reserved 9.5.4 video timing registers [80 - 103], [50-67] indexes in the range [80 - 103] control the generically named video timing registers, including the image pan/tilt parameters a nd line & field length of the sensor. the registers are as follows: 1. line length. 2. x-offset of region of interest. bit function default comment 2:0 ms dark line pixel offset 0 this register contains a ?xed offset that can be applied to the digitised pixels in the dig- ital output coding block. the offset is a 2s complement number, giving an offset range -1024,+1023. if this external offset cancellation is to be applied then it register[46], bits[1:0] should be reprogrammed to 2b1x. 7:0 ls dark line pixel offset table 48 : [44 - 45], [3c-3d] - dark pixel offset bit function default comment 1:0 dark line offset cancellation 01 x0 - accumulate dark pixels, calculate dark pixel average and report, but dont apply anything to data stream 01 - accumulate dark pixels, calculate dark pixel average and report and apply internally calculated offset to data stream 11 - accumulate dark pixels, calculate dark pixel average and report, but apply an externally calculated offset 2 number of dark lines used all dark lines /use half the number of dark lines. 0 the dark line offset cancellation algorithm can opt to only use pixels from dark lines that are preceeded by another dark line, i.e line choose only line 306 from line 305 and line 306. 5:3 reserved 6 use narrow dark offset deadband yes /no 1 the deadband describes a range of dark pixel averages that will force the leaky integrator algorithm to hold its current value. 0 - target +/- 4 codes 1 - target +/- 2 codes 7 unused 0 table 49 : [46], [3e] - dark pixel cancellation setup register
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 77/105 cd5410-6410f-3-0.fm 3. y-offset of region of interest. 4. frame length. the length of a line is specified in a number of pixel clocks, whereas the length of a field is specified in a number of lines. the range of some parameter values is limited and any value programmed out-with this range will be clipped to the maximum allowed. the x-offset and y-offset are only programmable if the user has selected the pan tilt qcif mode. if the other video modes are selected then the x-offset and y-offset registers will have pre-programmed values applied, but they cannot be changed. the x-offset and y-offset default values are chosen such that the output image, regardless of video mode selected, will be centered within the pixel array, (see section 3.2 for details). [103], [67] - unused [104-105], [68-69] - reserved [106-107], [6a-6b] - unused [108-109], [6c-6d] - reserved [110-111], [6e-6f] - unused 9.5.5 system registers -addresses [112 - 127], [70-7f] this page of the serial interface i2c address space comprises a wide range of registers including the registers required to control the black offset cancellation algorithm, enable test modes and also control various aspects of the analogue behavior of the sensor. index 10 index 16 bit function default comment 80-81 50-51 reserved 82 52 1:0 line length msb value 415 minimum mode dependent maximum = 1023 actual line duration in pixel periods is line length programmed +1. 83 53 7:0 line length lsb value 84 - 86 54-56 reserved 87 57 0 x-offset msb value 5 minimum (positive) value = 1 88 58 7:0 x-offset lsb value 89 59 0 y-offset msb value 3 minimum (positive) value = 1 90 5a 7:0 y-offset lsb value 91 - 96 5b-60 reserved 97 61 1:0 field length msb value 319 minimum mode dependent maximum = 1023 actual field duration in line periods is field length programmed +1. 98 62 7:0 field length lsb value 99-102 63-66 reserved table 50 : video timing registers
vv5410 & vv6410 serial control bus cd5410-6410f-3-0.fm commercial in confidence 78/105 [112 - 113], [70-71] - black pixel offset [114], [72] - black pixel cancellation setup register [115], [73] - unused [116], [74] - reserved [117 - 118], [75-76] - control registers 0 and 1- cr0 and cr1 although we give the user access to the following 5registers it is not anticipated that the contents of these registers will have to be altered. if the user does wish to alter any of the register bits then they are strongly advised to contact vibu before doing so . bit function default comment 2:0 ms black line pixel offset - 64 this register contains a ?xed offset that can be applied to the digitised pixels in the digital output coding block.the offset is a 2s complement number, giving an offset range -1024,+1023. if this external offset cancellation is to be applied then it register[114], bits[1:0] should be reprogrammed to 2b1x. 7:0 ls black line pixel offset table 51 : [112 - 113], [70-71] - black pixel offset bit function default comment 1:0 black line offset cancellation 01 x0 - accumulate black pixels, calculate black pixel average and report, but dont apply anything to data stream 01 - accumulate black pixels, calculate black pixel average and report and apply internally calculated offset to data stream 11 - accumulate black pixels, calculate black pixel average and report, but apply an externally calculated offset 4:2 reserved 100 the time constant controls the rate at which a change in the black level is corrected for. 5 use narrow black offset deadband yes /no 1 the deadband describes a range of pixel averages that will cause the leaky integrator algorithm to hold its current value. 0 - target +/- 4 codes 1 - target +/- 2 codes 7:6 unused 00 table 52 : [114], [72] - black offset cancellation setup bit function default comment 0 enable bit line clamp off /on 0 1 enable bit line test off /on 0 table 53 : [117], [75] - control register cr0
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 79/105 cd5410-6410f-3-0.fm [119] [77] - adc setup register as0 3:2 bit line white reference 0.7 v / 1.1 v / 1.5v / ext. 00 00 - 0.7v 01 - 1.1v 10 - 1.5v 11 - external 4 enable anti blooming off /on 0 5 power down - lvds input comparator off /on 0 powers down lvds input. cmos clock input may still be used. 6 power down - sram off /on 0 powers down sram comparator 7 power down - vccs off /on 0 powers down voltage controlled current source bit function default comment 0 stand-by off /on 0 powers down all analog circuitry with the exception of the band gap 1 power down - internal ramp generator off /on 0 2 power down - column adc off /on 0 powers down preamp and comparators 3 power down - cab regulator off /on 0 referred to in figures as pd_creg 4 power down - audio amplifier regulator off /on 0 referred to in figures as pd_areg 5 power down - vrt amplifier off /on 0 allows external vrt to be applied 6 ramp common mode voltage vrt-vtn /1.5v 0 0 - vrt-vtn ramp common mode voltage 1- 1.5v ramp common mode voltage 7 current boost to column comparator 75ua /50ua 0 0 - 75ua 1- 50ua table 54 : [118], [76] - control register cr1 bit function default comment 1:0 reserved 10 table 55 : [119], [77] - adc setup register as0 bit function default comment table 53 : [117], [75] - control register cr0
vv5410 & vv6410 serial control bus cd5410-6410f-3-0.fm commercial in confidence 80/105 2 enable voltage doubler off /on 0 it is recommended that this bit is set if the sensor is being used in a 3.3v supply environment 3 differential ramp enable off/ /on 1 ramp generator signal bpramp 4 view column/view vcmtcas vcmtcas /column 1 0 - view column voltage vx[363] 1- view vcmtcas 5 ramp viewing/column comparator test ramps /test comparator 0 0 -view ramps on cpos/cneg 1- input to test comparator 364 6 stepped ramp enable off /on 1 setting this bit enables a stepped ramp. clearing this bit enables a continuous ramp. 7 bit function default comment table 55 : [119], [77] - adc setup register as0
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 81/105 cd5410-6410f-3-0.fm [120], [78] - analog test register at0 [121], [79] - audio ampli?er setup register at1 [122-125] ,[7a-7d] - unused [126-127] ,[7e-7f] - reserved bit function default comment 0 sram test enable off /on 0 2:1 vrt voltage 2.2v / 2.5v / 2.8v / ext. 00 00 - vrt = 2.2v 01 - vrt = 2.5v 10 - vrt = 2.8v 11 - reserved 4:3 lineint & readint phasing 00 00 - 0 degree phase delay 01 - 90 degree phase delay 10 - 180 degree phase delay 11 - 270 degree phase delay 7:5 unused 000 table 56 : [120], [78] - analog test register at0 bit function default comments 0 first stage gain 1 0 - 0db 1 - 30db 1 second stage gain[1] 0 gain[1] gain[0] - gain(db) 0 0 - 0db 0 1 - 6db 1 0 - 12db 1 1 - 18db 2 second stage gain[0] 0 3 power down 1 0 - powered up 1 - power down 4 output select 0 0 - single ended 1 - differential 5 current boost 0 0 - 1ma output drive in output buffers 1 - 2ma output drive in output buffers 7:6 unused 00 table 57 : [121], [79] - audio ampli?er setup register at1
vv5410 & vv6410 serial control bus cd5410-6410f-3-0.fm commercial in confidence 82/105 9.6 types of messages this section gives guidelines on the basic operations to read data from and write data to the serial interface. the serial interface supports variable length messages. a message may contain no data bytes, one data byte or many data bytes. this data can be written to or read from common or different locations within the sensor. the range of instructions available are detailed below. ? write no data byte, only sets the index for a subsequent read message. ? single location data write or read for monitoring (real time control) ? multiple location read or write for fast information transfers. examples of these operations are given below. a full description of the internal registers is given in the previous section. fo r all examples the slave address used is 32 10 for writing and 33 10 for reading. the write address includes the read/write bit (the lsb) set to zero while this bit is set in the read address. 9.6.1 single location, single data write. when a random value is written to the sensor, the message will look like this: in this example, the fineh exposure register (index = 32 10 ) is set to 85 10 . the r/w bit is set to zero for writing and the inc bit (msbit of the index byte) is set to zero to disable automatic increment of the index after writing the value. the address index is preserved and may be used by a subsequent read. the write message is terminated with a stop condition from the master. 9.6.2 single location, single data read. a read message always contains the index used to get the first byte. this example assumes that a write message has already taken place and the residual index value is 32 10 . a value of 85 10 is read from the fineh exposure register. note that the read message is terminated with a negative acknowledge ( a) from the master: it is not guaranteed that the master will be able to issue a stop condition at any other time during a read message. this is because if the data sent by the slave is all zeros, the sda line cannot rise, which is part of the stop condition. figure 38 : single location, single write. s 32 10 a0 32 10 a85 10 a p start device ack address index data stop inc figure 39 : single location, single read. s 33 10 a0 32 10 a85 10 a p start device ack address index data stop master reads from slave, acknowledging each byte
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 83/105 cd5410-6410f-3-0.fm 9.6.3 no data write followed by same location read. when a location is to be read, but the value of the stored index is not known, a write message with no data byte must be writte n first, specifying the index. the read message then completes the message sequence. to avoid relinquishing the serial to bus to another master a repeated start condition is asserted between the write and read messages, i.e. no stop condition is asserted. in this example, the gain value (index = 36 10 ) is read as 15 10 : as mentioned in the previous example, the read message is terminated with a negative acknowledge ( a) from the master. 9.6.4 same location multiple data write. it may be desirable to write a succession of data to a common location. this is useful when the status of a bit (e.g. auto-load ) must be toggled. the message sequence indexes sf_setup register 108. if bit 0 is toggled high, low this will initiate a fresh auto-load. this is achieved by writing two consecutive data bytes to the sensor. there is no requirement to re-send the register index before each data byte. 9.6.5 same location multiple data read when an exposure related value ( fineh, finel, coarseh, coarse l , gain or clk_div ) is written, it takes effect on the output at the beginning of the next video frame, (remember that the application of the gain value is a frame later than the other exposure parameters). to signal the consumption of the written value, a flag is set when any of the exposure or gain registers are writt en and is reset at the start of the next frame. this flag appears in status0 register and may be monitored by the bus master. to speed up reading from this location, the sensor will repeatedly transmit the current value of the register, as long as the mast er acknowledges each byte read. in the below example, a fineh exposure value of 0 is written, the status register is addressed (no data byte) and then constantly read until the master terminates the read message. figure 40 : no data write followed by same location read. s a sr a a a p 33 10 36 10 33 10 36 10 15 10 a 0 0 no data write read index and data sa a a 32 10 21 10 4 10 0 10 a 0 write to pin_mapping figure 41 : same location multiple data write. 4 10 p toggle control bit
vv5410 & vv6410 serial control bus cd5410-6410f-3-0.fm commercial in confidence 84/105 9.6.6 multiple location write if the automatic increment bit is set (msb of the index byte), then it is possible to write data bytes to consecutive adjacent internal registers, (i.e. 23,24,25,26 etc), without having to send explicit indexes prior to sending each data byte. an auto-increment write to the exposure registers with their default values is shown in the following example, where we write 17 10 to the pin_mapping register[21] and 193 10 to the data format register[22]. . 9.6.7 multiple location read in the same manner, multiple locations can be read with a single read message. in this example the index is written first, to ensure the exposure related registers are addressed and then all six are read. note: a stop condition is not required after the final negative acknowledge from the master, the sensor will terminate the communication upon receipt of the negative acknowledge from the master. sa 0 10 a a a 32 10 33 10 32 10 0 10 a 0 sr a a a a 33 10 0 10 1 10 1 10 1 10 a 0 sr write ?nel with zero address the status0 register a 1 10 0 10 a read continuously... ...until ?ag reset p figure 42 : same location multiple data read. sa 17 10 a aa 32 10 21 10 193 10 1 incremental write p figure 43 : multiple location write. incremental read sa a 32 10 32 10 1 sr 33 10 aa 32 10 1 ?neh a ap ?nel coarseh coarsel gain clk_div a a a a no data write incremental read figure 44 : multiple location read.
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 85/105 cd5410-6410f-3-0.fm 9.7 serial interface timing parameter symbol min. max. unit scl clock frequency fscl 0 100 khz bus free time between a stop and a start tbuf 2 - us hold time for a repeated start thd;sta 80 - ns low period of scl tlow 320 - ns high period of scl thigh 160 - ns set-up time for a repeated start tsu;sta 80 - ns data hold time thd;dat 0 - ns data set-up time tsu;dat 0 - ns rise time of scl, sda tr - 300 ns fall time of scl, sda tf - 300 ns set-up time for a stop tsu;sto 80 - ns capacitive load of each bus line (scl, sda) cb - 200 pf table 58 : serial interface timing characteristics sda scl thd;sta tr thigh tf tsu;dat thd;dat tsu;sta tsu;sto ... ... thd;sta tlow tbuf stop start stop start figure 45 : serial interface timing characteristics
vv5410 & vv6410 clock signal cd5410-6410f-3-0.fm commercial in confidence 86/105 10. clock signal vv5410/vv6410 system clock is supplied from an external clock source directly driving the clki pin. the clock pad has an integral schmitt buffer to filter noise from the clock source. please note that there is no support for an external resonator c ircuit. the clock signal must be a square wave with, ideally a 50% ( 10%) mark:space ratio, although a non-ideal mark:space ratio can be tolerated, please contact stmicroelectronics for details. the maximum input clock frequency for the module is 24.0 mhz. if the 24mhz crystal is preferred then the user must select the pre-clock divide by 1.5 option such that the bulk of the internal logic is driven by a 16mhz clock, see serial interface, register 16 10 , data_format. vv5410/vv6410 clk figure 46 : cmos clock source clki clock source clock division
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 87/105 cd5410-6410f-3-0.fm 11. other features 11.1 audio ampli?er vv5410/vv6410 contains an on-chip audio amplifier which can be configured via the serial interface. the amplifier may also be powered down via the serial interface. the following document outlines the implementation of audio circuitry on the vv5410/vv6410 sensor. 11.1.1 audio ampli?er con?guration the audio circuit is controlled through a single eight bit register on the vv5410/vv6410. this includes bits for power down, output select, first and second stage gains and current boosting. table 59 describes the functionality of the control register bits. the first stage provides a gain of 0db or 30db using a low noise amplifier design. the reference is provided from the on-chip bandgap voltage. this is buffered by a cut down version of the low-noise amplifier used in the first gain stage. the output of the first gain stage is fed to two output amplifiers. these can be configured with a 1ma or 2ma output drive current. the inverting gain stage provides an additional gain between 0db and 18db. the output of the inverting gain stage may be routed through the other output buffer to provide two single ended outputs. otherwise, the inverted and non-inverted outputs provide a fully differential output signal. some more circuit specifications may be found in table 60. bit function default comments 0 first stage gain 1 0 - 0db 1 - 30db 1 second stage gain[1] 0 gain[1] gain[0] - gain(db) 0 0 - 0db 0 1 - 6db 1 0 - 12db 1 1 - 18db 2 second stage gain[0] 0 3 power down 0 0 - powered up 1 - power down 4 output select 0 0 - single ended 1 - differential 5 current boost 0 0 - 1ma output drive in output buffers 1 - 2ma output drive in output buffers 7:6 unused table 59 : control register summary for vv5410/vv6410 audio circuit.
vv5410 & vv6410 other features cd5410-6410f-3-0.fm commercial in confidence 88/105 11.1.2 aud3v3 (audio supply regulator) 11.1.3 audio ampli?er parameters symbol parameter min typical max units aud3v3 regulated supply (no external load) 3.13 3.3 3.46 v aud3v3_ld regulated supply vdrop (current load 20ma) -50 mv aud3v3_sus regulated supply (suspend mode) off v zaud3v3_sus output impedance in suspend mode tbc k w psrr power supply rejection versus vin -48 db table 60 : audio circuit speci?cation symbol parameter min typical max units vain audio regulator input voltage v bg v r in input impedance 100 k w gain1 ist stage (28db) gain accuracy +/-0.5 db gain2 2nd stage (0,6,12,18db) gain accuracy 1 1. 2nd stage gain is only available on aoutn with the audio ampli?er in differential mode +/-0.2 db gmatch differential output mode gain matching (0db) (28db)( 0.2 0.5 db out_max output clipping level 2 1.6 2.2 vpp out_dc output dc voltage 1.1 1.22 1.3 v d-out_dc differential dc offset (aoutn-aoutp) 20 100 mv rout output impedance 2 k w thd thd (includes noise) vin = 20mvpp, f-1khz, gain =28db 0.2 % snr signal to noise ratio (1khz) (10khz) 3 65 75 db psrr power supply rejection ratio from vin -55 db lfc low frequency cutoff (cin=100nf) 15 hz xtalk video crosstalk to audio outputs (gain = 28db) -56 db table 61 : audio ampli?er parameters
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 89/105 cd5410-6410f-3-0.fm 11.1.4 audio ampli?er bandwidth 1 the audio circuit can be bandwidth limited to a first order, through the use of minimum external circuitry. the two outputs, aoutp and aoutn, require compensation capacitors that may also be used to define the bandwidth of the circuit. in addition, the inclusion of a resistor (microphone biasing) and decoupling capacitor at the input allows a first order high p ass filter to be realised. this can easily be designed to remove frequencies below 50hz/60hz (mains electricity noise). 11.2 voltage regulators vv5410/vv6410 contains three on-chip voltage regulators, two of which are capable of being powered-down via the serial interface. the third regulator, controlling the band gap references is never powered down. the band gap circuitry is extremely low power consuming only 30 m a. 11.2.1 regulator for digital system the output of the regulator, reg3v3, powers the digital logic and can power an external co-processor. the regulator is powered up by default. the regulator has its own discrete power supply and can source a load of 300 m a -> 150ma and will regulate to 3.0v 10% from an input range of 4-6v. when vv5410/vv6410 is in the usb compatible suspend mode, the clocks to the digital logic are removed to limit power consumption to approximately 80 m a. if an external 3.3v supply is available, this regulator may be overdriven by an external 3.3v supply to directly power the logic. this voltage regulator is never powered down. 11.2.2 regulator for audio ampli?er the output of the regulator for the audio amplifier, aud3v3, drives the load resistor for the microphone and the audio pre- amplifier. as this regulator is capable of being powered-down via the serial interface, all control signals from the digital lo gic are low during low power/standby. this regulator will be powered up by default. 11.2.3 regulator for video supply/analogue core the output of the regulator for the video supply,vid3v3, powers the analog core. this regulator is capable of being powered- down via the serial interface but will be powered up by default. note that the sensor will be in low power mode initially and therefore 11.3 valid supply voltage con?gurations the power supplies to the vv5410 and vv6410 sensors can be configured such that the sensor will operate in a number of systems: ? usb system (sensor will regulate the nominal 5v supply to 3v3 internally) with optional bjt to provide power for a companion chip. ? direct drive the sensor with 3v3 (internal voltage regulators will be powered down in this mode). the next 2figures will detail the options described above: 2. minimum dynamic range includes dcout (i.e. vclip- out_dc is greater than vppmin/2) 3. assumes 10 m f bypass capacitors on all supplies and well separated supplies and grounds 1. each audio output must have a capacitor (ccomp) connected to ground to avoid any oscillation compensation capacitor (nf) 3db bandwidth units 1 175 khz 10 41 khz 100 4.2 khz table 62 : compensation capacitor values
vv5410 & vv6410 other features cd5410-6410f-3-0.fm commercial in confidence 90/105 digital regulator 5v vout audio regulator 5v vout analog regulator 5v vout audio amp analog core digital logic vvl410 pd_areg pd_creg pd vbus reg3v3 vddcore aud3v3 vid3v3 vbase 220nf 220nf bandgap vbg vbg vbg 100nf voltage doubler 100nf vddhi vbg vddio vin (5v) (powered up) (powered up) figure 47 : usb power setup 27uf 390 key: 5v0 supply from usb cable regulated 3v3 digital regulator 5v vout audio regulator 5v vout analog regulator 5v vout audio amp analog core digital logic vvl410 pd_areg pd_creg pd vbus reg3v3 vddcore aud3v3 vid3v3 dvdd vbase 220nf 220nf bandgap vbg vbg vbg 100nf voltage doubler 100nf vddhi vbg (3.3v) vddio avdd (3.3v) n/c n/c (powered down) (powered down) figure 48 : direct drive @3v3 setup key: analogue 3v3 supply digital 3v3 supply
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 91/105 cd5410-6410f-3-0.fm 11.4 programmable pins the fst and qck pins can be re-configured to follow the values of bits 1 and 2 in the serial interface.register pin_mapping . this is to allow remote control of a electro-mechanical system, maybe two different crop settings, in a remote camera head via the serial interface. supply usb system 3.3v-only system vbus supply from usb cable 3.3v direct drive vddio connect to vreg3v3 3.3v direct drive vddcore connect to vreg3v3 3.3v direct drive vreg3v3 optionally populate external bjt for added drive bjt not populated vid3v3 generated by internal regulator internal regulator powered down aud3v3 generated by internal regulator internal regulator powered down table 63 : sensor voltage supply summary
vv5410 & vv6410 characterisation details cd5410-6410f-3-0.fm commercial in confidence 92/105 12. characterisation details 12.1 vv5410/vv6410 ac/dc speci?cation table 64 : vv5410/6410 dc speci?cation 12.2 vv5410/vv6410 optical characterisation data parameter comment units image format 356 x 292 pixels (pal/cif) 306 x 244 pixels (ntsc) 180 x 148 pixels (qcif) - pixel size 7.5 x 6.9 m m technology 0.5 m m 3 level metal cmos - array format cif - exposure control range 81 (minimum exposure period 3 m s and maximum exposure period is 33ms) 1 1. we assume cif (30fps) mode, input clock of 16mhz and internal clock divisor of 1. db supply voltage 3.0-6.0 dc +/-10% v operating temp. range 0 - 40 o c v ol_max 2 2. this is worst case reading. device outputs had signi?cant capacitive loading and supply voltage reduced to 2v7 0.512 v v oh_min 3 3. this is worst case reading. device outputs had signi?cant capacitive loading and supply voltage reduced to 2v7 2.054 v v i_maxl 4 4. this is worst case reading. device outputs had signi?cant capacitive loading and supply voltage reduced to 2v7 0.683 v v ih_min 5 5. this is worst case reading. device outputs had signi?cant capacitive loading and supply voltage reduced to 2v7 2.237 v serial interface frequency range 0-100khz optical parameter min typical max units dark current - 46 - mv/sec average sensitivity - 2.1 - v/lux.sec fixed pattern noise (fpn) - 1.74 - mv vertical fixed pattern noise (vfpn) - 1.2 - mv random noise - 1.17 - mv sensor snr - c.56 - db shading (gross) - 0.9 - mv table 65 : vv5410/vv6410 optical characterisation data
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 93/105 cd5410-6410f-3-0.fm 12.2.1 noise parameters and dark current various noise parameters are measured on the 410 device as follows: ? fixed pattern noise (fpn) ? vertical fixed pattern noise (vfpn) ? random noise ? fine shading ? gross shading the parameters will be described in more detail below along with the data produced by the characterisation programme. 12.2.2 blooming blooming is a phenomenon that does not affect cmos sensors in the same way as ccd imagers are afflicted. with a ccd blooming can cause an entire column/columns to flood and saturate. cmos imagers are however affected by a different type of saturation. if an intense light source, (e.g. maglite torch), is shone at very close proximity to the image sensor the pixel sampling mechanism will break down and rather than displaying a saturated white light a black image will occur. the 410 pixel architecture uses correlated double sampling (cds) to help reduce noise in the system. the pixel is read normally first, yielding the true integrated signal information, then the pixel is reset and very quickly read for a second time. this n ormally yields black information - as the pixel has had no exposure time - that can be subtracted from the signal from the first read. this subtraction will remove much of the noise from the pixel leaving only the useful signal information. in an example where a pixel has saturated in both the first and the second reads due to an intense light source. when the noise cancellation subtraction operation is then performed the result is close to zero signal from the pixel therefore resulting in t he displayed black image. we do not perform any test measurements for this phenomenon. 12.2.3 dark current this is defined as the rate at which the average pixel voltage increases over time with the device not illuminated. the dark current will be measured at a gain setting of 4 and a clock divisor of 16 at a fixed temperature and will be expressed in mv. 12.2.4 fixed pattern noise the fpn of an image sensor is the average pixel non-temporal noise divided by the average pixel voltage. the illumination source will be white light that has been ir filtered, producing a diffuse uniform illumination at the surface of the sensor pac kage. the fpn will be calculated at coarse exposure settings of 0,10,150,250 and 302 with gain set to 1. 10 frames are grabbed and averaged to produce a temporally independent frame before each calculation. fpn will be expressed in mv. 12.2.5 vertical fixed pattern noise vfpn describes the spatial noise in an image sensor related to patterns with a vertical orientation. the vfpn is defined as the standard deviation over all columns of the average pixel voltage for each column determined at zero exposure and zero illumination. vfpn will be expressed in mv. 12.2.6 random noise random noise is the temporal noise component within the image. random noise will be expressed in mv. 12.2.7 shading this describes how average pixel values per block change across the image sensor array. for fine shading calculations the image sensor array is split into 30 pixel by 30 pixel blocks. an average value is then calculated for each block and the averag es are then compared across the whole device. the blocks are increased in size to 60 pixels by 60 pixels for the gross shading calculation. shading will be expressed in mv.
vv5410 & vv6410 characterisation details cd5410-6410f-3-0.fm commercial in confidence 94/105 12.3 vv5410/vv6410 power consumption table 66 : vv5410/6410 current consumption in different modes 12.4 digital input pad pull-up and pull-down strengths operating condition current consumption low power mode current consumption 5.6ma sleep mode current consumption 1 1. estimated ?gures - this parameter was not measured during ?nal characterisation 18ma suspend mode current consumption (with clkip disabled) 85ua normal operating mode current consumption 2 2. measured while device is clocked at 16mhz and streaming cif video at 30fps 26.2ma pad type pads min current max current library pulldown suspend 35ua 52ua library pullup scl, sda, oeb 25ua 42ua custom pullup resetb 66ua 250ua table 67 : pad pull-up/pull-down strengths
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 95/105 cd5410-6410f-3-0.fm 13. pixel defect speci?cation 13.1 pixel fault de?nitions please find the pixel notation described in figure 49 below. for the purposes of the test the 3x3 array describes 9 bayer pixels of a common colour, i.e. all the pixels will either be red, green or blue. the pixel under test is x . figure 49 : pixel numbering notation 13.2 stuck at white pixel fault a pixel is said to be stuck at white - it can also be referred to as hot - if it is saturated (pixel output at maximum) eve n with no incident light and exposure set to zero. 13.3 stuck at black pixel fault a pixel is said to be stuck at black - it can also be referred to as dead - if the pixel output is zero even if the pixel i s fully exposed to incident light. 13.4 column / row faults a line of continuous pixel fails of length > 3 will be described as a row fault in the x-direction and a column fault in the y-direction. if the array contains more than 1 row or column fault and the defective pixels overlap as shown in figure 50 then this fault is described as a double row or double column fault respectively. the minimum overlap is 1 pixel. a defective pixel is indicated by x and a good pixel by p. figure 50 : double column fault in figure 51 there are 2 column faults however there is no overlap between the 2 columns therefore there are 2 single column faults but no double column faults. [0] [1] [2] [7] x [3] [6] [5] [4] n n+1 x p x p x p xx p x p x p x
vv5410 & vv6410 pixel defect specification cd5410-6410f-3-0.fm commercial in confidence 96/105 figure 51 : single column faults 13.5 image array blemishes the automatic test programme rejects any sensors that contain blemishes referred to as blobs and clusters (please see below for definitions of these terms) as they cannot be successfully defect corrected by st coprocessor devices. up to 120 single pixel faults can be corrected and sensors meeting this criteria will pass this part of the test programme. 13.5.1 cluster de?nition a failing pixel at x with a failing pixel at position [0] or [1] or [2] or [3] or [4] or [5] or [6] or [7] or any combination of these 8 positions except the case where all positions are defective. this is a special case and is described below. in the example in figure 52 there are additional pixel fails in positions [3] and [7]. figure 52 : cluster example blob (special case of cluster):- a failing pixel at position x with failing pixels at position [0],[1],[2],[3],[4],[5],[6] and [7] as in figure 53 below: figure 53 : blob example n n+1 x p x p x p x p p x p x p x p x [0] [1] [2] [ x ] x [ x ] [6] [5] [4] [ x ][ x ][ x ] [ x ] x [ x ] [ x ][ x ][ x ]
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 97/105 cd5410-6410f-3-0.fm single pixel:- a failing pixel with no immediate failing same colour neighbours. pixels at position [0],[1],[2],[3],[4],[5],[6] and [7] are all valid pixels. please see figure 54 below. figure 54 : isolated pixel fail 13.5.2 summary pass criteria clusters blobs row fails (inc doubles) column fails (inc doubles) single pixel fails notes 1 1. if there is a non-zero number of clusters, blobs or row/column faults and greater than 120 single pixel defects then the device will be rejected and classed as a fail. 0 0 0 0 <=120 pass table 68 : sensor pixel defect pass criteria [0] [1] [2] [7] x [3] [6] [5] [4]
vv5410 & vv6410 pinout and pin descriptions cd5410-6410f-3-0.fm commercial in confidence 98/105 14. pinout and pin descriptions 14.1 36pin clcc pinout map figure 55 : 36 pin clcc package pin assignment name pin number type description power supplies avss 10 gnd core analog ground and reference supplies. resetb d[0] lst/d[5] fst/d[6] vddcore/ vbus vbg vrt aoutp vddhi oeb clki 7 8 6 5 4 3 2 1 9 10 11 12 13 14 15 16 17 19 20 21 22 23 24 25 26 27 28 29 32 33 34 35 36 d[3] d[4] aud3v3 aoutn vbase avss 18 30 31 vbltw d[1] vid3v3 ain vsscore vssio sramvss d[2] qck sda suspend vddio d[7] vbloom reg3v3 scl porb
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 99/105 cd5410-6410f-3-0.fm sramvss 17 gnd in-column sram analog ground. vddcore/ reg3v3 34 pwr digital logic power. vddio 33 pwr digital pad ring power. vsscore 22 gnd digital logic ground. vssio 23 gnd digital pad ring ground. vid3v3 11 pwr on-chip video supply voltage regulator output aud3v3 3 pwr on-chip audio amplifier voltage regulator output analog signals vbg 1 oa internally generated bandgap reference voltage 1.22v vddhi 9 ia voltage doubler output, 4.6v -> 4.8v vbase 35 oa drive for base of external bipolar vbus 36 ia incoming power supply 3.3 -> 6v ain 4 ia analog input to audio amplifier aoutp 5 oa analog output of audio amplifier (positive) aoutn 6 oa analog output of audio amplifier (negative) porb 13 od power-on reset (bar) output. digital video interface d[4] d[3] d[2] d[1] d[0] 27 26 25 24 20 odt tri-stateable 5-wire output data bus. - d[4] is the most significant bit. - d[4:0] have programmable drive strengths 2, 4 and 6 ma qck 32 odt tri-stateable data qualification clock. lst/d[5] 28 odt tri-stateable line start output may be configured as tri-stateable output data bit 5 d[5]. fst/d[6] 29 odt tri-stateable frame start signal. may be configured as tri-stateable output data bit 6 d[6]. d[7] 31 odt tri-stateable data wire (ms data bit). may be configured as tri-stateable output data bit 6 d[6]. oeb 16 id digital output (tri-state) enable. digital control signals name pin number type description
vv5410 & vv6410 pinout and pin descriptions cd5410-6410f-3-0.fm commercial in confidence 100/105 resetb 21 id - system reset. active low. may be configured as system sync. active low. suspend 12 id - usb suspend mode control signal. active high if this feature is not required then the support circuit must pull the pin to ground. the combination of an active high signal and pull up pad was chosen to limit current drawn by the device while in suspend mode. serial interface scl 15 bi - serial bus clock (input only). sda 14 bi - serial bus data (bidirectional, open drain). system clocks clki 30 id schmitt buffered clock input or lvds positive clock input key a analog input d digital input oa analog output id - digital input with internal pull-up bi bidirectional id digital input with internal pull-down bi - bidirectional with internal pull-up od digital output bi bidirectional with internal pull-down odt tri-stateable digital output name pin type description analog signals vbloom 8 oa anti-blooming pixel reset voltage 1 1. this pin has been removed from the production bonding diagram vbltw 7 oa bitline test white level reference 2 2. this pin has been removed from the production bonding diagram vrt 2 ia pixel reset voltage 3 3. this pin has been removed from the production bonding diagram name pin number type description
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 101/105 cd5410-6410f-3-0.fm 15. package details (36pin clcc) revno revision note date 2 1 3 4 5 6 78 ecn no. 10.67 - 0.13 +0.30 2.67 2.02 8.13 0.13 1.02 0.13 40 places r 0.15 notes. 1. die is optically centred. 2. refractive index of glass is ~1.52. 3. distance to optical surface of die. 4. pixel area of sensor. pin 1 pin 5 pin 6 a a 1.16 0.09 (note 3) 2.15 - 0.26 +0.16 0.60 - 0.10 0.00 1.55 0.16 a-a (8 : 1) a pin locations changed, tolerance added to o/all dims 14/7/99 b package now 36 pin 20/7/99 c 1.03 0.13 was 1.03 0.08 2/8/99 d 1.16 dim tolerance revised 15/10/99
vv5410 & vv6410 recommended vv5410/6410 support circuit cd5410-6410f-3-0.fm commercial in confidence 102/105 16. recommended vv5410/6410 support circuit
cmos sensor; customer datasheet, rev 3.0, 28 september 2000 vv5410 & vv6410 commercial in confidence 103/105 cd5410-6410f-3-0.fm 17. evaluation kits (evks) it is highly recommended that an evaluation kit (evk) is used for initial evaluation and design-in of the vv5410/6410. a vv5410/ vv6410 evaluation kit can now be ordered. please contact stmicroelectronics for details.
vv5410 & vv6410 ordering details cd5410-6410f-3-0.fm commercial in confidence 104/105 18. ordering details part number description vv5410c036 36pin clcc packaged, microlensed cif monochrome sensor vv6410c036 36pin clcc packaged, microlensed cif colourmos sensor stv0657 yuv/rgb coprocessor stv0672 usb companion coprocessor stv0680b-001 digital stills companion coprocessor STV-5410-R01 reference design board for vv6410c036 stv-6410-r01 reference design board for vv6410c036 stv-usb/cif-r01 reference design board for vv6410c036 & stv0672 stv-yuv/cif-r02 reference design board for vv6410c036 & stv0657-001 stv-dca/cif-r01 reference design board for vv6410c036 & stv0680b-001 stv-5410/5500-e01 sensor only evaluation kit for vv6410c036 & vv6500-c048 stv-6410/6500-e01 sensor only evaluation kit for vv6410c036 & vv6500-c048 table 69 : vv6410/vv5410 ordering details
commercial in confidence 105/105 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics the st logo is a registered trademark of stmicroelectronics ? 2000 stmicroelectronics - all rights reserved imaging division cd5410-6410f-3-0.fm cmos sensor; customer datasheet, rev 3.0,28 september 2000 cd5410-6410f www.st.com asiapacific.imaging@st.com centraleurope.imaging@st.com france.imaging@st.com japan.imaging@st.com nordic.imaging@st.com southerneurope.imaging@st.com ukeire.imaging@st.com usa.imaging@st.com

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